{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T07:00:13Z","timestamp":1767855613492,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":56,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,12,5]],"date-time":"2015-12-05T00:00:00Z","timestamp":1449273600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF","award":["0953246, 1212962, 1320531, 1409723"],"award-info":[{"award-number":["0953246, 1212962, 1320531, 1409723"]}]},{"name":"Intel Science and Technology Center for Cloud Computing"},{"name":"Semiconductor Research Corporation"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830820","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T13:38:13Z","timestamp":1452519493000},"page":"267-280","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":100,"title":["Gather-scatter DRAM"],"prefix":"10.1145","author":[{"given":"Vivek","family":"Seshadri","sequence":"first","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Mullins","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amirali","family":"Boroumand","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Phillip B.","family":"Gibbons","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael A.","family":"Kozuch","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Todd C.","family":"Mowry","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"http:\/\/download.intel.com\/design\/processor\/manuals\/253665.pdf","unstructured":"Intel 64 and IA-32 Architectures Software Developer's Manual. http:\/\/download.intel.com\/design\/processor\/manuals\/253665.pdf , Vol. 1 , Chap . 3.7. Intel 64 and IA-32 Architectures Software Developer's Manual. http:\/\/download.intel.com\/design\/processor\/manuals\/253665.pdf, Vol. 1, Chap. 3.7."},{"key":"e_1_3_2_1_2_1","volume-title":"http:\/\/h18000.www1.hp.com\/cpq-alphaserver\/technology\/literature\/21264hrm.pdf","year":"1999","unstructured":"Alpha 21264 Microprocessor Hardware Reference Manual. http:\/\/h18000.www1.hp.com\/cpq-alphaserver\/technology\/literature\/21264hrm.pdf , 1999 . Alpha 21264 Microprocessor Hardware Reference Manual. http:\/\/h18000.www1.hp.com\/cpq-alphaserver\/technology\/literature\/21264hrm.pdf, 1999."},{"key":"e_1_3_2_1_3_1","volume-title":"https:\/\/www.gartner.com\/doc\/2657815\/hybrid-transactionanalytical-processing-foster -opportunities","year":"2014","unstructured":"Hybrid Transaction\/Analytical Processing Will Foster Opportunities for Dramatic Business Innovation. https:\/\/www.gartner.com\/doc\/2657815\/hybrid-transactionanalytical-processing-foster -opportunities , 2014 . Hybrid Transaction\/Analytical Processing Will Foster Opportunities for Dramatic Business Innovation. https:\/\/www.gartner.com\/doc\/2657815\/hybrid-transactionanalytical-processing-foster -opportunities, 2014."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2008.13"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.381947"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.36"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/520549.822749"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2011.17"},{"key":"e_1_3_2_1_11_1","unstructured":"K. Chandrasekar C. Weis Y. Li S. Goossens M. Jung O. Naji B. Akesson N. Wehn and K. Goossens. DRAMPower: Opensource DRAM Power & Energy Estimation Tool. http:\/\/www.drampower.info.  K. Chandrasekar C. Weis Y. Li S. Goossens M. Jung O. Naji B. Akesson N. Wehn and K. Goossens. DRAMPower: Opensource DRAM Power & Energy Estimation Tool. http:\/\/www.drampower.info."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835946"},{"key":"e_1_3_2_1_13_1","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally W.","year":"2003","unstructured":"W. Dally and B. Towles . Principles and Practices of Interconnection Networks . Morgan Kaufmann Publishers Inc ., San Francisco, CA, USA, 2003 . W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2003."},{"key":"e_1_3_2_1_14_1","volume-title":"ICPP","author":"Frailong J. M.","year":"1985","unstructured":"J. M. Frailong , W. Jalby , and J. Lenfant . XOR-Schemes: A Flexible Data Organization in Parallel Memories . In ICPP , 1985 . J. M. Frailong, W. Jalby, and J. Lenfant. XOR-Schemes: A Flexible Data Organization in Parallel Memories. In ICPP, 1985."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/115952.115959"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/144953.145006"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485930"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.14778\/1921071.1921077"},{"key":"e_1_3_2_1_19_1","volume-title":"http:\/\/hstore.cs.brown.edu\/documentation\/deployment\/anti-caching\/","year":"2015","unstructured":"H-Store. Anti-Caching. http:\/\/hstore.cs.brown.edu\/documentation\/deployment\/anti-caching\/ , 2015 . H-Store. Anti-Caching. http:\/\/hstore.cs.brown.edu\/documentation\/deployment\/anti-caching\/, 2015."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362684"},{"key":"e_1_3_2_1_21_1","unstructured":"JEDEC. DDR4 SDRAM Standard. http:\/\/www.jedec.org\/standards-documents\/docs\/jesd79-4a 2013.  JEDEC. DDR4 SDRAM Standard. http:\/\/www.jedec.org\/standards-documents\/docs\/jesd79-4a 2013."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.14778\/1454159.1454211"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"crossref","DOI":"10.1109\/9780470544426","volume-title":"DRAM Circuit Design: Fundamental and High-speed Topics","author":"Keeth B.","year":"2007","unstructured":"B. Keeth , R. J. Baker , B. Johnson , and F. Lin . DRAM Circuit Design: Fundamental and High-speed Topics . Wiley-IEEE Press , 2007 . B. Keeth, R. J. Baker, B. Johnson, and F. Lin. DRAM Circuit Design: Fundamental and High-speed Topics. Wiley-IEEE Press, 2007."},{"key":"e_1_3_2_1_24_1","volume-title":"HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu , and M Harchol-Balter . ATLAS : A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers . In HPCA , 2010 . Y. Kim, D. Han, O. Mutlu, and M Harchol-Balter. ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers. In HPCA, 2010."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_26_1","volume-title":"ISCA","author":"Kim Y.","year":"2012","unstructured":"Y. Kim , V. Seshadri , D. Lee , J. Liu , and O. Mutlu . A Case for Exploiting Subarray-level Parallelism (SALP) in DRAM . In ISCA , 2012 . Y. Kim, V. Seshadri, D. Lee, J. Liu, and O. Mutlu. A Case for Exploiting Subarray-level Parallelism (SALP) in DRAM. In ISCA, 2012."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522354"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.71.0015"},{"key":"e_1_3_2_1_31_1","volume-title":"ISCA","author":"Liu J.","year":"2012","unstructured":"J. Liu , B. Jaiyen , R. Veras , and O. Mutlu . RAIDR: Retention-Aware Intelligent DRAM Refresh . In ISCA , 2012 . J. Liu, B. Jaiyen, R. Veras, and O. Mutlu. RAIDR: Retention-Aware Intelligent DRAM Refresh. In ISCA, 2012."},{"key":"e_1_3_2_1_32_1","volume-title":"http:\/\/docs.memsql.com\/4.0\/ref\/datatypes\/","author":"Datatypes QL.","year":"2015","unstructured":"MemS QL. Datatypes . http:\/\/docs.memsql.com\/4.0\/ref\/datatypes\/ , 2015 . MemSQL. Datatypes. http:\/\/docs.memsql.com\/4.0\/ref\/datatypes\/, 2015."},{"key":"e_1_3_2_1_33_1","volume-title":"SS","author":"Moscibroda T.","year":"2007","unstructured":"T. Moscibroda and O. Mutlu . Memory Performance Attacks: Denial of Memory Service in Multi-core Systems . In SS , 2007 . T. Moscibroda and O. Mutlu. Memory Performance Attacks: Denial of Memory Service in Multi-core Systems. In SS, 2007."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10030"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192014"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/115952.115961"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_40_1","volume-title":"ISCA","author":"Seshadri V.","year":"2014","unstructured":"V. Seshadri , A. Bhowmick , O. Mutlu , P. Gibbons , M. Kozuch , and T. Mowry . The Dirty-block Index . In ISCA , 2014 . V. Seshadri, A. Bhowmick, O. Mutlu, P. Gibbons, M. Kozuch, and T. Mowry. The Dirty-block Index. In ISCA, 2014."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192072"},{"key":"e_1_3_2_1_43_1","volume-title":"VLDB","author":"Shamgunov N.","year":"2014","unstructured":"N. Shamgunov . The MemSQL In-Memory Database System . In VLDB , 2014 . N. Shamgunov. The MemSQL In-Memory Database System. In VLDB, 2014."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"e_1_3_2_1_45_1","volume-title":"VLDB","author":"Stonebraker M.","year":"2005","unstructured":"M. Stonebraker , D. J. Abadi , A. Batkin , X. Chen , M. Cherniack , M. Ferreira , E. Lau , A. Lin , S. Madden , E. O'Neil , P. O'Neil , A. Rasin , N. Tran , and S. Zdonik . C-store: A Column-oriented DBMS . In VLDB , 2005 . M. Stonebraker, D. J. Abadi, A. Batkin, X. Chen, M. Cherniack, M. Ferreira, E. Lau, A. Lin, S. Madden, E. O'Neil, P. O'Neil, A. Rasin, N. Tran, and S. Zdonik. C-store: A Column-oriented DBMS. In VLDB, 2005."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974655"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815983"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/143369.143403"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.42"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380850"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000100"},{"key":"e_1_3_2_1_52_1","volume-title":"ISCA","author":"Yoon D. H.","year":"2012","unstructured":"D. H. Yoon , M. K. Jeong , M. Sullivan , and M. Erez . The Dynamic Granularity Memory System . In ISCA , 2012 . D. H. Yoon, M. K. Jeong, M. Sullivan, and M. Erez. The Dynamic Granularity Memory System. In ISCA, 2012."},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.966490"},{"key":"e_1_3_2_1_54_1","volume-title":"ISCA","author":"Zhang T.","year":"2014","unstructured":"T. Zhang , K. Chen , C. Xu , G. Sun , T. Wang , and Y. Xie . Half-DRAM: A High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation . In ISCA , 2014 . T. Zhang, K. Chen, C. Xu, G. Sun, T. Wang, and Y. Xie. Half-DRAM: A High-bandwidth and Low-power DRAM Architecture from the Rethinking of Fine-grained Activation. In ISCA, 2014."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771792"},{"key":"e_1_3_2_1_56_1","first-page":"5630096","article-title":"Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order","author":"Zuravleff W. K.","year":"1997","unstructured":"W. K. Zuravleff and T. Robinson . Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order . Patent 5630096 , 1997 . W. K. Zuravleff and T. Robinson. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order. Patent 5630096, 1997.","journal-title":"Patent"}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","location":"Waikiki Hawaii","acronym":"MICRO-48","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830820","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830820","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:40Z","timestamp":1750225720000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830820"}},"subtitle":["in-DRAM address translation to improve the spatial locality of non-unit strided accesses"],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":56,"alternative-id":["10.1145\/2830772.2830820","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830820","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}