{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:46:18Z","timestamp":1772725578008,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":45,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,12,5]],"date-time":"2016-12-05T00:00:00Z","timestamp":1480896000000},"content-version":"vor","delay-in-days":366,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-14-1-0148"],"award-info":[{"award-number":["FA9550-14-1-0148"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217553"],"award-info":[{"award-number":["CCF-1217553"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006502","name":"Defense Sciences Office, DARPA","doi-asserted-by":"publisher","award":["N66001-14-1-4040"],"award-info":[{"award-number":["N66001-14-1-4040"]}],"id":[{"id":"10.13039\/100006502","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["HR0011-13-2-0005"],"award-info":[{"award-number":["HR0011-13-2-0005"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830828","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T08:38:13Z","timestamp":1452501493000},"page":"76-88","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["MORC"],"prefix":"10.1145","author":[{"given":"Tri M.","family":"Nguyen","sequence":"first","affiliation":[{"name":"Princeton University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Wentzlaff","sequence":"additional","affiliation":[{"name":"Princeton University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1816021"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917729"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/2523262"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1360612.1360617"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871610"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.89"},{"key":"e_1_3_2_1_8_1","first-page":"88","volume-title":"ISSCC 2008","author":"Bell S.","year":"2008","unstructured":"S. Bell et al., \"Tile64 - processor: A 64-core soc with mesh interconnect,\" in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 88--598, Feb 2008."},{"key":"e_1_3_2_1_9_1","volume-title":"Acceleration interfaces and architecture,\" in Proceedings of Hot Chips Symposium","author":"Ramey C.","year":"2011","unstructured":"C. Ramey, \"Tile-gx100 manycore processor: Acceleration interfaces and architecture,\" in Proceedings of Hot Chips Symposium, 2011."},{"key":"e_1_3_2_1_10_1","unstructured":"G. E. Moore \"Cramming More Components Onto Integrated Circuits \" Electronics Apr. 1965."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/232974.232983"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268591"},{"key":"e_1_3_2_1_13_1","unstructured":"S. Thoziyoor N. Muralimanohar and N. P. Jouppi \"CACTI 5.0 \" HP Laboratories Technical Report 2007."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.121"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_16_1","unstructured":"TECHNICK.NET \"PCB Impedance Calculator \" http:\/\/www.technick.net\/public\/code\/cp_dpage.php?aiocp_dp=util_pcb_imp_microstrip."},{"key":"e_1_3_2_1_17_1","unstructured":"Micron Technology \"DDR3 System-Power Calculator \" www.micron.com\/support\/power-calc."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006719"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540715"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.4"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155670"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665696"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2012.31"},{"key":"e_1_3_2_1_26_1","unstructured":"I. Pavlov \"LZMA SDK \" www.7-zip.org\/sdk.html 2007."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"L. P. Deutsch \"GZIP file format specification version 4.3 \" 1996.","DOI":"10.17487\/rfc1952"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339660"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/48012.48037"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.131"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"L. P. Deutsch \"DEFLATE compressed data format specification version 1.3 \" 1996.","DOI":"10.17487\/rfc1951"},{"key":"e_1_3_2_1_33_1","unstructured":"AHA \"AHA Data Compression \" http:\/\/www.aha.com\/data-compression\/."},{"key":"e_1_3_2_1_34_1","unstructured":"Indra \"Indra Products \" http:\/\/www.indranetworks.com\/products.html."},{"key":"e_1_3_2_1_35_1","first-page":"116","volume-title":"2014 IEEE International Symposium on","author":"Fu Y.","year":"2014","unstructured":"Y. Fu and D. Wentzlaff, \"PriME: A parallel and distributed simulator for thousand-core chips,\" in Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on, pp. 116--125, IEEE, 2014."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"e_1_3_2_1_37_1","volume-title":"Pinballs: Portable and Shareable User-level Checkpoints for Reproducible Analysis and Simulation,\" in Proceedings of the Workshop on Reproducible Research Methodologies (REPRODUCE)","author":"Patil H.","year":"2014","unstructured":"H. Patil and T. E. Carlson, \"Pinballs: Portable and Shareable User-level Checkpoints for Reproducible Analysis and Simulation,\" in Proceedings of the Workshop on Reproducible Research Methodologies (REPRODUCE), 2014."},{"key":"e_1_3_2_1_38_1","volume-title":"Frequent pattern compression: A significance-based compression scheme for L2 caches,\" Dept. Comp. Scie","author":"Alameldeen A. R.","year":"2004","unstructured":"A. R. Alameldeen and D. A. Wood, \"Frequent pattern compression: A significance-based compression scheme for L2 caches,\" Dept. Comp. Scie., Univ. Wisconsin-Madison, Tech. Rep, vol. 1500, 2004."},{"key":"e_1_3_2_1_39_1","volume-title":"http:\/\/www.glue.umd.edu\/ajaleel\/workload","author":"Jaleel A.","year":"2010","unstructured":"A. Jaleel, \"Memory characterization of workloads using instrumentation-driven simulation,\"Web Copy: http:\/\/www.glue.umd.edu\/ajaleel\/workload, 2010."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.43"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.73"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.41"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.452.0271"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.28"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370864"}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","location":"Waikiki Hawaii","acronym":"MICRO-48","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830828","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830828","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830828","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:29:35Z","timestamp":1763458175000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830828"}},"subtitle":["a manycore-oriented compressed cache"],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":45,"alternative-id":["10.1145\/2830772.2830828","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830828","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}