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Archit. Code Optim."],"published-print":{"date-parts":[[2016,1,7]]},"abstract":"<jats:p>\n                    3D-stacked DRAM alleviates the limited memory bandwidth bottleneck that exists in modern systems by leveraging\n                    <jats:italic toggle=\"yes\">through silicon vias<\/jats:italic>\n                    (TSVs) to deliver higher external memory channel bandwidth. Today\u2019s systems, however, cannot fully utilize the higher bandwidth offered by TSVs, due to the limited\n                    <jats:italic toggle=\"yes\">internal<\/jats:italic>\n                    bandwidth within each layer of the 3D-stacked DRAM. We identify that the bottleneck to enabling higher bandwidth in 3D-stacked DRAM is now the\n                    <jats:italic toggle=\"yes\">global bitline interface<\/jats:italic>\n                    , the connection between the DRAM row buffer and the peripheral IO circuits. The global bitline interface consists of a limited and expensive set of wires and structures, called\n                    <jats:italic toggle=\"yes\">global bitlines<\/jats:italic>\n                    and\n                    <jats:italic toggle=\"yes\">global sense amplifiers<\/jats:italic>\n                    , whose high cost makes it difficult to simply scale up the bandwidth of the interface\n                    <jats:italic toggle=\"yes\">within<\/jats:italic>\n                    a single DRAM layer in the 3D stack. We alleviate this bandwidth bottleneck by exploiting the observation that several global bitline interfaces already exist\n                    <jats:italic toggle=\"yes\">across<\/jats:italic>\n                    the multiple DRAM layers in current 3D-stacked designs, but only a fraction of them are enabled at the same time.\n                  <\/jats:p>\n                  <jats:p>\n                    We propose a new 3D-stacked DRAM architecture, called\n                    <jats:italic toggle=\"yes\">Simultaneous Multi-Layer Access<\/jats:italic>\n                    (SMLA), which increases the internal DRAM bandwidth by accessing multiple DRAM layers concurrently, thus making much greater use of the bandwidth that the TSVs offer. To avoid channel contention, the DRAM layers must coordinate with each other when simultaneously transferring data. We propose two approaches to coordination, both of which deliver four times the bandwidth for a four-layer DRAM, over a baseline that accesses only one layer at a time. Our first approach, Dedicated-IO,\n                    <jats:italic toggle=\"yes\">statically partitions<\/jats:italic>\n                    the TSVs by assigning each layer to a dedicated set of TSVs that operate at a higher frequency. Unfortunately, Dedicated-IO requires a nonuniform design for each layer (increasing manufacturing costs), and its DRAM energy consumption scales linearly with the number of layers. Our second approach, Cascaded-IO, solves both issues by instead\n                    <jats:italic toggle=\"yes\">time multiplexing<\/jats:italic>\n                    all of the TSVs across layers. Cascaded-IO reduces DRAM energy consumption by lowering the operating frequency of higher layers. Our evaluations show that SMLA provides significant performance improvement and energy reduction across a variety of workloads (55%\/18% on average for multiprogrammed workloads, respectively) over a baseline 3D-stacked DRAM, with low overhead.\n                  <\/jats:p>","DOI":"10.1145\/2832911","type":"journal-article","created":{"date-parts":[[2016,1,7]],"date-time":"2016-01-07T09:04:54Z","timestamp":1452157494000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":95,"title":["Simultaneous Multi-Layer Access"],"prefix":"10.1145","volume":"12","author":[{"given":"Donghyuk","family":"Lee","sequence":"first","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saugata","family":"Ghose","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gennady","family":"Pekhimenko","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samira","family":"Khan","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University, Pittsburgh PA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,1,6]]},"reference":[{"key":"e_1_2_2_1_1","doi-asserted-by":"publisher","unstructured":"Bryan Black Murali Annavaram Ned Brekelbaum John DeVale Lei Jiang Gabriel H. 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