{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:25:35Z","timestamp":1763724335521,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,11,16]],"date-time":"2015-11-16T00:00:00Z","timestamp":1447632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2016,1,7]]},"abstract":"<jats:p>\n            Five percent to 25% of power could be wasted before it is delivered to the computational resources on a die, due to inefficiencies of voltage regulators and resistive loss. The power delivery could benefit if, at the same power, the delivered voltage increases and the current decreases. This article presents\n            <jats:italic>CoreUnfolding<\/jats:italic>\n            , a technique that leverages voltage Stacking to improve power delivery efficiency. Our experiments show that about 10% system-wide power can be saved, the voltage regulator area can be reduced by 30%,\n            <jats:italic>di<\/jats:italic>\n            \/\n            <jats:italic>dt<\/jats:italic>\n            improves 49%, and the power pin count is reduced by 40% (\u2248 20% reduction in packaging costs), with negligible performance degradation.\n          <\/jats:p>","DOI":"10.1145\/2835178","type":"journal-article","created":{"date-parts":[[2015,11,18]],"date-time":"2015-11-18T13:42:28Z","timestamp":1447854148000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Managing Mismatches in Voltage Stacking with CoreUnfolding"],"prefix":"10.1145","volume":"12","author":[{"given":"Ehsan K.","family":"Ardestani","sequence":"first","affiliation":[{"name":"UC Santa Cruz, Santa Cruz, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rafael Trapani","family":"Possignolo","sequence":"additional","affiliation":[{"name":"UC Santa Cruz, Santa Cruz, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose Luis","family":"Briz","sequence":"additional","affiliation":[{"name":"Universidad Zaragoza, Zaragoza - Espa\u00f1a"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose","family":"Renau","sequence":"additional","affiliation":[{"name":"UC Santa Cruz, Santa Cruz, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,11,16]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_2_1_2_1","volume-title":"Proceedings of the 2014 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC\u201914)","author":"Burton E. A.","year":"2014","unstructured":"E. A. Burton , G. Schrom , F. Paillet , J. Douglas , W. J. Lambert , K. Radhakrishnan , and M. J. Hill . 2014. FIVR -- Fully integrated voltage regulators on 4th generation Intel\u00aeCore\u2122SoCs . In Proceedings of the 2014 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC\u201914) . 432--439. DOI:http:\/\/dx.doi.org\/10.1109\/APEC. 2014 .6803344 10.1109\/APEC.2014.6803344 E. A. Burton, G. Schrom, F. Paillet, J. Douglas, W. J. Lambert, K. Radhakrishnan, and M. J. Hill. 2014. FIVR -- Fully integrated voltage regulators on 4th generation Intel\u00aeCore\u2122SoCs. In Proceedings of the 2014 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC\u201914). 432--439. DOI:http:\/\/dx.doi.org\/10.1109\/APEC.2014.6803344"},{"doi-asserted-by":"publisher","key":"e_1_2_1_3_1","DOI":"10.1109\/INTLEC.2014.6972231"},{"volume-title":"Proceedings of the 2010 IEEE Symposium on VLSI Circuits (VLSIC\u201910)","author":"Chang L.","unstructured":"L. Chang , R. K. Montoye , B. L. Ji , A. J. Weger , K. G. Stawiasz , and R. H. Dennard . 2010. A fully-integrated switched-capacitor 2 1 voltage converter with regulation capability and 90&percnt; efficiency at 2.3 A\/mm 2 . In Proceedings of the 2010 IEEE Symposium on VLSI Circuits (VLSIC\u201910) . IEEE, 55--56. L. Chang, R. K. Montoye, B. L. Ji, A. J. Weger, K. G. Stawiasz, and R. H. Dennard. 2010. A fully-integrated switched-capacitor 2 1 voltage converter with regulation capability and 90&percnt; efficiency at 2.3 A\/mm 2. In Proceedings of the 2010 IEEE Symposium on VLSI Circuits (VLSIC\u201910). IEEE, 55--56.","key":"e_1_2_1_4_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_5_1","DOI":"10.1145\/2000064.2000067"},{"doi-asserted-by":"publisher","key":"e_1_2_1_6_1","DOI":"10.1109\/TCAD.2010.2062811"},{"doi-asserted-by":"publisher","key":"e_1_2_1_7_1","DOI":"10.1145\/1077603.1077651"},{"doi-asserted-by":"publisher","key":"e_1_2_1_8_1","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_2_1_9_1","volume-title":"18th Annual IEEE Applied Power Electronics Conference and Exposition","volume":"1","author":"Huang W.","year":"2003","unstructured":"W. Huang , G. Schuellein , and D. Clavette . 2003. A scalable multiphase buck converter with average current share bus . In 18th Annual IEEE Applied Power Electronics Conference and Exposition , 2003 (APEC\u201903), Vol. 1 . IEEE, 438--443. W. Huang, G. Schuellein, and D. Clavette. 2003. A scalable multiphase buck converter with average current share bus. In 18th Annual IEEE Applied Power Electronics Conference and Exposition, 2003 (APEC\u201903), Vol. 1. IEEE, 438--443."},{"unstructured":"Linear Technology Inc. 2012. Dual 4A Per Channel DC\/DC uModule Regulator. Retrieved from http:\/\/www.linear.com\/product\/LTM4614.  Linear Technology Inc. 2012. Dual 4A Per Channel DC\/DC uModule Regulator. Retrieved from http:\/\/www.linear.com\/product\/LTM4614.","key":"e_1_2_1_10_1"},{"unstructured":"Linear Technology Inc. 2014. Dual 8A Per Channel DC\/DC uModule Regulator. Retrieved from http:\/\/www.linear.com\/product\/LTM4616.  Linear Technology Inc. 2014. Dual 8A Per Channel DC\/DC uModule Regulator. Retrieved from http:\/\/www.linear.com\/product\/LTM4616.","key":"e_1_2_1_11_1"},{"unstructured":"Linear Technology Inc. 2013. Ultralow Vin 15A DC\/DC uModule Regulator. http:\/\/www.linear.com\/product\/LTM4611.  Linear Technology Inc. 2013. Ultralow Vin 15A DC\/DC uModule Regulator. http:\/\/www.linear.com\/product\/LTM4611.","key":"e_1_2_1_12_1"},{"unstructured":"Intel Inc. 2014. Desktop 4th Generation Intel\u00aeCore\u2122Processor Family Desktop Intel Pentium\u00aeProcessor Family and Desktop Intel\u00aeCeleron\u00aeProcessor Family - Datasheet. http:\/\/www.intel.com\/content\/www\/us\/en\/processors\/core\/4th-gen-core-family-desktop-vol-1-datasheet.html.  Intel Inc. 2014. Desktop 4th Generation Intel\u00aeCore\u2122Processor Family Desktop Intel Pentium\u00aeProcessor Family and Desktop Intel\u00aeCeleron\u00aeProcessor Family - Datasheet. http:\/\/www.intel.com\/content\/www\/us\/en\/processors\/core\/4th-gen-core-family-desktop-vol-1-datasheet.html.","key":"e_1_2_1_13_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_14_1","DOI":"10.1109\/TVLSI.2003.821548"},{"doi-asserted-by":"publisher","key":"e_1_2_1_15_1","DOI":"10.1109\/2.869367"},{"doi-asserted-by":"publisher","key":"e_1_2_1_16_1","DOI":"10.1109\/HPCA.2013.6522340"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 2013 28th Annual IEEE Applied Power Electronics Conference and Exposition (APEC\u201913)","author":"Kesarwani K.","year":"2013","unstructured":"K. Kesarwani , C. Schaef , C. R. Sullivan , and J. T. Stauth . 2013. A multi-level ladder converter supporting vertically-stacked digital voltage domains . In Proceedings of the 2013 28th Annual IEEE Applied Power Electronics Conference and Exposition (APEC\u201913) . 429--434. DOI:http:\/\/dx.doi.org\/10.1109\/APEC. 2013 .6520245 10.1109\/APEC.2013.6520245 K. Kesarwani, C. Schaef, C. R. Sullivan, and J. T. Stauth. 2013. A multi-level ladder converter supporting vertically-stacked digital voltage domains. In Proceedings of the 2013 28th Annual IEEE Applied Power Electronics Conference and Exposition (APEC\u201913). 429--434. DOI:http:\/\/dx.doi.org\/10.1109\/APEC.2013.6520245"},{"volume-title":"Proceedings of the 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201911)","author":"Kim W.","unstructured":"W. Kim , D. M. Brooks , and G. Y. Wei . 2011. A fully-integrated 3-level DC\/DC converter for nanosecond-scale DVS with fast shunt regulation . In Proceedings of the 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201911) . IEEE, 268--270. W. Kim, D. M. Brooks, and G. Y. Wei. 2011. A fully-integrated 3-level DC\/DC converter for nanosecond-scale DVS with fast shunt regulation. In Proceedings of the 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201911). IEEE, 268--270.","key":"e_1_2_1_18_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_19_1","DOI":"10.1109\/JSSC.2011.2169309"},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture","author":"Kim W.","year":"2008","unstructured":"W. Kim , M. S. Gupta , G.-Y. Wei , and D. Brooks . 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators . In Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture , 2008 (HPCA\u201908). IEEE, 123--134. W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks. 2008. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of the IEEE 14th International Symposium on High Performance Computer Architecture, 2008 (HPCA\u201908). IEEE, 123--134."},{"doi-asserted-by":"publisher","key":"e_1_2_1_21_1","DOI":"10.1145\/2333660.2333746"},{"doi-asserted-by":"publisher","key":"e_1_2_1_22_1","DOI":"10.1109\/VLSIC.2015.7231306"},{"doi-asserted-by":"publisher","key":"e_1_2_1_23_1","DOI":"10.1145\/2627369.2627605"},{"doi-asserted-by":"publisher","key":"e_1_2_1_24_1","DOI":"10.5555\/1356802.1356895"},{"doi-asserted-by":"crossref","unstructured":"G. V. Piqu\u00e9 and H. J. Bergveld. 2012. State-of-the-art of integrated switching power converters. In Analog Circuit Design. Springer 259--281.  G. V. Piqu\u00e9 and H. J. Bergveld. 2012. State-of-the-art of integrated switching power converters. In Analog Circuit Design. Springer 259--281.","key":"e_1_2_1_25_1","DOI":"10.1007\/978-94-007-1926-2_13"},{"doi-asserted-by":"crossref","unstructured":"M. Popovich A. V. Mezhiba and E. G. Friedman. 2007. Power Distribution Networks with On-Chip Decoupling Capacitors. Springer.   M. Popovich A. V. Mezhiba and E. G. Friedman. 2007. Power Distribution Networks with On-Chip Decoupling Capacitors. Springer.","key":"e_1_2_1_26_1","DOI":"10.1007\/978-0-387-71601-5"},{"doi-asserted-by":"publisher","key":"e_1_2_1_27_1","DOI":"10.1109\/JSSC.2006.874314"},{"doi-asserted-by":"publisher","key":"e_1_2_1_28_1","DOI":"10.1109\/JSSC.2004.842861"},{"doi-asserted-by":"publisher","key":"e_1_2_1_29_1","DOI":"10.1109\/JSSC.2010.2076550"},{"doi-asserted-by":"publisher","key":"e_1_2_1_30_1","DOI":"10.1109\/TPEL.2015.2426572"},{"volume-title":"Proceedings of the 2010 International Conference on Energy Aware Computing (ICEAC\u201910)","author":"Shenoy P. S.","unstructured":"P. S. Shenoy , V. T. Buyukdegirmenci , A. M. Bazzi , and P. T. Krein . 2010. System level trade-offs of microprocessor supply voltage reduction . In Proceedings of the 2010 International Conference on Energy Aware Computing (ICEAC\u201910) . IEEE, 1--4. P. S. Shenoy, V. T. Buyukdegirmenci, A. M. Bazzi, and P. T. Krein. 2010. System level trade-offs of microprocessor supply voltage reduction. In Proceedings of the 2010 International Conference on Energy Aware Computing (ICEAC\u201910). IEEE, 1--4.","key":"e_1_2_1_31_1"},{"key":"e_1_2_1_32_1","volume-title":"Proceedings of the 2011 International Conference on Energy Aware Computing (ICEAC\u201911)","author":"Shenoy P. S.","year":"2011","unstructured":"P. S. Shenoy , S. Zhang , R. A. Abdallah , P. T. Krein , and N. R. Shanbhag . 2011b. Overcoming the power wall: Connecting voltage domains in series . In Proceedings of the 2011 International Conference on Energy Aware Computing (ICEAC\u201911) . 1--6. DOI:http:\/\/dx.doi.org\/10.1109\/ICEAC. 2011 .6403629 10.1109\/ICEAC.2011.6403629 P. S. Shenoy, S. Zhang, R. A. Abdallah, P. T. Krein, and N. R. Shanbhag. 2011b. Overcoming the power wall: Connecting voltage domains in series. In Proceedings of the 2011 International Conference on Energy Aware Computing (ICEAC\u201911). 1--6. DOI:http:\/\/dx.doi.org\/10.1109\/ICEAC.2011.6403629"},{"volume-title":"Proceedings of the 2011 International Conference on Energy Aware Computing (ICEAC\u201911)","author":"Shenoy P. S.","unstructured":"P. S. Shenoy , I. Fedorov , T. Neyens , and P. T. Krein . 2011a. Power delivery for series connected voltage domains in digital circuits . In Proceedings of the 2011 International Conference on Energy Aware Computing (ICEAC\u201911) . IEEE, 1--6. P. S. Shenoy, I. Fedorov, T. Neyens, and P. T. Krein. 2011a. Power delivery for series connected voltage domains in digital circuits. In Proceedings of the 2011 International Conference on Energy Aware Computing (ICEAC\u201911). IEEE, 1--6.","key":"e_1_2_1_33_1"},{"unstructured":"Infineon Technologies. 2013. High Performance DrMos TDA21220. http:\/\/www.infineon.com\/cms\/en\/product\/power\/dc-dc-converter\/dc-dc-integrated-power-stage\/drmos-integrated-power-stage\/TDA21220\/productType.html?productType=db3a3044243b532e0124de3165386adc.  Infineon Technologies. 2013. High Performance DrMos TDA21220. http:\/\/www.infineon.com\/cms\/en\/product\/power\/dc-dc-converter\/dc-dc-integrated-power-stage\/drmos-integrated-power-stage\/TDA21220\/productType.html?productType=db3a3044243b532e0124de3165386adc.","key":"e_1_2_1_34_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_35_1","DOI":"10.1109\/ISSCC.2014.6757354"},{"volume-title":"Solid Tantalum Surface Mount Chip Capacitors. Vishay Sprague","author":"Sprague V.","unstructured":"V. Sprague . 2013. Solid Tantalum Surface Mount Chip Capacitors. Vishay Sprague , Santa Clara, CA . V. Sprague. 2013. Solid Tantalum Surface Mount Chip Capacitors. Vishay Sprague, Santa Clara, CA.","key":"e_1_2_1_36_1"},{"doi-asserted-by":"publisher","key":"e_1_2_1_38_1","DOI":"10.1145\/223982.223990"},{"doi-asserted-by":"publisher","key":"e_1_2_1_39_1","DOI":"10.1145\/1412587.1412591"},{"doi-asserted-by":"publisher","key":"e_1_2_1_40_1","DOI":"10.1109\/TED.2006.884077"},{"doi-asserted-by":"publisher","key":"e_1_2_1_41_1","DOI":"10.1109\/63.892832"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2835178","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2835178","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:09Z","timestamp":1750225689000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2835178"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11,16]]},"references-count":40,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2016,1,7]]}},"alternative-id":["10.1145\/2835178"],"URL":"https:\/\/doi.org\/10.1145\/2835178","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"type":"print","value":"1544-3566"},{"type":"electronic","value":"1544-3973"}],"subject":[],"published":{"date-parts":[[2015,11,16]]},"assertion":[{"value":"2015-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-11-16","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}