{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T08:23:38Z","timestamp":1759134218462,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,12,22]],"date-time":"2015-12-22T00:00:00Z","timestamp":1450742400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["CCF-1547980"],"award-info":[{"award-number":["CCF-1547980"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2016,1,7]]},"abstract":"<jats:p>Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high performance, supporting the PGAS memory model is associated with penalties that can hinder PGAS\u2019s potential for scalability and speed of execution. This is because mapping the PGAS memory model to the underlying system requires a mapping process that is done in software, thereby introducing substantial overhead for shared accesses even when they are local. Compiler optimizations have not been sufficient to offset this overhead. On the other hand, manual code optimizations can help, but this eliminates the productivity edge of PGAS. This article proposes a processor microarchitecture extension that can perform such address mapping in hardware with nearly no performance overhead. These extensions are then availed to compilers through extensions to the processor instructions. Thus, the need for manual optimizations is eliminated and the productivity of PGAS languages is unleashed. Using Unified Parallel C (UPC), a PGAS language, we present a case study of a prototype compiler and architecture support. Two different implementations of the system were realized. The first uses a full-system simulator, gem5, which evaluates the overall performance gain of the new hardware support. The second uses an FPGA Leon3 soft-core processor to verify implementation feasibility and to parameterize the cost of the new hardware. The new instructions show promising results on all tested codes, including the NAS Parallel Benchmark kernels in UPC. Performance improvements of up to 5.5\u00d7 for unmodified codes, sometimes surpassing hand-optimized performance, were demonstrated. We also show that our four-core FPGA prototype requires less than 2.4% of the overall chip\u2019s area.<\/jats:p>","DOI":"10.1145\/2842686","type":"journal-article","created":{"date-parts":[[2015,12,22]],"date-time":"2015-12-22T14:11:19Z","timestamp":1450793479000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Enabling PGAS Productivity with Hardware Support for Shared Address Mapping"],"prefix":"10.1145","volume":"12","author":[{"given":"Olivier","family":"Serres","sequence":"first","affiliation":[{"name":"George Washington University, Washington, DC"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdullah","family":"Kayi","sequence":"additional","affiliation":[{"name":"Parallel Computing Lab, Intel Corporation, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmad","family":"Anbar","sequence":"additional","affiliation":[{"name":"George Washington University, Washington, DC"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tarek","family":"El-Ghazawi","sequence":"additional","affiliation":[{"name":"George Washington University, Washington, DC"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2014.34"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/225830.224443"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2012.6322869"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2005.219"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/838237.838436"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303318"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1177\/1094342007078442"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1103845.1094852"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/782814.782825"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the Workshop on Languages and Compilers and Parallel Computing (LCPC\u201914)","author":"Dalton Barnaby","year":"2014","unstructured":"Barnaby Dalton , Gabriel Tanase , Michail Alvanos , George Almasi , and Ettore Tiotto . 2014 . Memory management techniques for exploiting RDMA in PGAS languages . In Proceedings of the Workshop on Languages and Compilers and Parallel Computing (LCPC\u201914) . Barnaby Dalton, Gabriel Tanase, Michail Alvanos, George Almasi, and Ettore Tiotto. 2014. Memory management techniques for exploiting RDMA in PGAS languages. In Proceedings of the Workshop on Languages and Compilers and Parallel Computing (LCPC\u201914)."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2010.5491777"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2716320"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2012.64"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the Workshop on Productivity and Performance in High-End Computing (P-PHEC\u201906)","author":"Ebcioglu Kemal","year":"2006","unstructured":"Kemal Ebcioglu , Vivik Sarkar , Tarek El-Ghazawi , and John Urbanic . 2006 . An experiment in measuring the productivity of three parallel programming languages . In Proceedings of the Workshop on Productivity and Performance in High-End Computing (P-PHEC\u201906) . IEEE, Los Alamitos, CA. Kemal Ebcioglu, Vivik Sarkar, Tarek El-Ghazawi, and John Urbanic. 2006. An experiment in measuring the productivity of three parallel programming languages. In Proceedings of the Workshop on Productivity and Performance in High-End Computing (P-PHEC\u201906). IEEE, Los Alamitos, CA."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/762761.762821"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2006.02.002"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/1214527"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/645535.657163"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470851"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627373.2627380"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MIXDES.2006.1706585"},{"key":"e_1_2_1_25_1","first-page":"12","article-title":"Efficient address translation. Interner Bericht. Universit\u00e4t Karlsruhe","volume":"2000","author":"Mueller Matthias M.","year":"2000","unstructured":"Matthias M. Mueller . 2000 . Efficient address translation. Interner Bericht. Universit\u00e4t Karlsruhe , Fakult\u00e4t f\u00fcr Informatik 2000 , 12 . Matthias M. Mueller. 2000. Efficient address translation. Interner Bericht. Universit\u00e4t Karlsruhe, Fakult\u00e4t f\u00fcr Informatik 2000, 12.","journal-title":"Fakult\u00e4t f\u00fcr Informatik"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/248209.237144"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.279"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.10"},{"key":"e_1_2_1_29_1","doi-asserted-by":"crossref","DOI":"10.2172\/862127","volume-title":"UPC Language Specifications V1.2. (May","author":"UPC Consortium","year":"2005","unstructured":"UPC Consortium . 2005. UPC Language Specifications V1.2. (May 2005 ). UPC Consortium. 2005. UPC Language Specifications V1.2. (May 2005)."},{"key":"e_1_2_1_30_1","volume-title":"Retrieved","author":"UPC","year":"2014","unstructured":"UPC NPB. 2014 . UPC NAS Parallel Benchmarks threads.seas.gwu.edu\/sites\/npb-upc . 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