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Archit. Code Optim."],"published-print":{"date-parts":[[2016,1,7]]},"abstract":"<jats:p>Static multi-issue machines, such as traditional Very Long Instructional Word (VLIW) architectures, move complexity from the hardware to the compiler. This is motivated by the ability to support high degrees of instruction-level parallelism without requiring complicated scheduling logic in the processor hardware. The simpler-control hardware results in reduced area and power consumption, but leads to a challenge of engineering a compiler with good code-generation quality.<\/jats:p>\n          <jats:p>Transport triggered architectures (TTA), and other so-called exposed datapath architectures, take the compiler-oriented philosophy even further by pushing more details of the datapath under software control. The main benefit of this is the reduced register file pressure, with a drawback of adding even more complexity to the compiler side.<\/jats:p>\n          <jats:p>\n            In this article, we propose an\n            <jats:italic>Integer Linear Programming (ILP)<\/jats:italic>\n            -based instruction scheduling model for TTAs. The model describes the architecture characteristics, the particular processor resource constraints, and the operation dependencies of the scheduled program. The model is validated and measured by compiling application kernels to various TTAs with a different number of datapath components and connectivity. In the best case, the cycle count is reduced to 52% when compared to a heuristic scheduler. In addition to producing shorter schedules, the number of register accesses in the compiled programs is generally notably less than those with the heuristic scheduler; in the best case, the ILP scheduler reduced the number of register file reads to 33% of the heuristic results and register file writes to 18%. On the other hand, as expected, the ILP-based scheduler uses distinctly more time to produce a schedule than the heuristic scheduler, but the compilation time is within tolerable limits for production-code generation.\n          <\/jats:p>","DOI":"10.1145\/2845082","type":"journal-article","created":{"date-parts":[[2015,12,22]],"date-time":"2015-12-22T14:11:19Z","timestamp":1450793479000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Integer Linear Programming-Based Scheduling for Transport Triggered Architectures"],"prefix":"10.1145","volume":"12","author":[{"given":"Tomi","family":"\u00c4ij\u00f6","sequence":"first","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pekka","family":"J\u00e4\u00e4skel\u00e4inen","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tapio","family":"Elomaa","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heikki","family":"Kultala","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jarmo","family":"Takala","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Finland"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2015,12,22]]},"reference":[{"key":"e_1_2_2_1_1","volume-title":"Proceedings of the International Conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems. 6--20","author":"Achterberg T.","unstructured":"T. Achterberg , T. Berthold , T. Koch , and K. Wolter . 2008. Constraint integer programming: A new approach to integrate CP and MIP . In Proceedings of the International Conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems. 6--20 . T. Achterberg, T. Berthold, T. Koch, and K. Wolter. 2008. Constraint integer programming: A new approach to integrate CP and MIP. In Proceedings of the International Conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems. 6--20."},{"key":"e_1_2_2_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.1676531"},{"key":"e_1_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/11823285_48"},{"key":"e_1_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0898-1221(97)00184-3"},{"key":"e_1_2_2_5_1","volume-title":"Lecture Notes in Computer Science","volume":"3133","author":"Cichon G.","unstructured":"G. Cichon , P. Robelly , H. Seidel , E. Mat\u00fas , M. Bronzel , and G. Fettweis . 2004. Synchronous transfer architecture (STA). In Computer Systems: Architectures Modeling and Simulation, A. D. Pimentel and S. Vassiliadis (Eds.) . Lecture Notes in Computer Science , Vol. 3133 . Springer-Verlag, Berlin, 343--352. DOI:http:\/\/dx.doi.org\/10.1007\/978-3-540-27776-7_36 10.1007\/978-3-540-27776-7_36 G. Cichon, P. Robelly, H. Seidel, E. Mat\u00fas, M. Bronzel, and G. Fettweis. 2004. Synchronous transfer architecture (STA). In Computer Systems: Architectures Modeling and Simulation, A. D. Pimentel and S. Vassiliadis (Eds.). Lecture Notes in Computer Science, Vol. 3133. Springer-Verlag, Berlin, 343--352. DOI:http:\/\/dx.doi.org\/10.1007\/978-3-540-27776-7_36"},{"key":"e_1_2_2_6_1","volume-title":"Finland. Retrieved","author":"Cilio A.","year":"2015","unstructured":"A. Cilio , H. Schot , and J. Janssen . 2006. Architecture Definition File: Processor Architecture Definition File Format for a New TTA Design Framework. Tampere University of Technology , Finland. Retrieved November 25, 2015 from http:\/\/tce.cs.tut.fi\/specs\/ADF.pdf. A. Cilio, H. Schot, and J. Janssen. 2006. Architecture Definition File: Processor Architecture Definition File Format for a New TTA Design Framework. Tampere University of Technology, Finland. Retrieved November 25, 2015 from http:\/\/tce.cs.tut.fi\/specs\/ADF.pdf."},{"key":"#cr-split#-e_1_2_2_8_1.1","doi-asserted-by":"crossref","unstructured":"H. Corporaal and J. Hoogerbrugge. 1995. Code generation for transport triggered architectures. In Code Generation for Embedded Processors P. Marwedel and G. Goossens (Eds.). Springer Berlin 240--259. DOI:http:\/\/dx.doi.org\/10.1007\/978-1-4615-2323-9_14 10.1007\/978-1-4615-2323-9_14","DOI":"10.1007\/978-1-4615-2323-9_14"},{"key":"#cr-split#-e_1_2_2_8_1.2","doi-asserted-by":"crossref","unstructured":"H. Corporaal and J. Hoogerbrugge. 1995. Code generation for transport triggered architectures. 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