{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T11:31:29Z","timestamp":1751369489910,"version":"3.41.0"},"reference-count":44,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,1,6]],"date-time":"2016-01-06T00:00:00Z","timestamp":1452038400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100011101","name":"Intel Collaborative Research Institute for Computational Intelligence","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100011101","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Viterbi Fellowship"},{"name":"Hasso-Plattner Institute"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2016,1,7]]},"abstract":"<jats:p>\n            GP-SIMD, a novel hybrid general-purpose SIMD architecture, addresses the challenge of data synchronization by in-memory computing, through combining data storage and massive parallel processing. In this article, we explore a resistive implementation of the GP-SIMD architecture. In resistive GP-SIMD, a novel resistive row and column addressable 4F\n            <jats:sup>2<\/jats:sup>\n            crossbar is utilized, replacing the modified CMOS 190F\n            <jats:sup>2<\/jats:sup>\n            SRAM storage previously proposed for GP-SIMD architecture. The use of the resistive crossbar allows scaling the GP-SIMD from few millions to few hundred millions of processing units on a single silicon die. The performance, power consumption and power efficiency of a resistive GP-SIMD are compared with the CMOS version. We find that PiM architectures and, specifically, GP-SIMD benefit more than other many-core architectures from using resistive memory. A framework for in-place arithmetic operation on a single multivalued resistive cell is explored, demonstrating a potential to become a building block for next-generation PiM architectures.\n          <\/jats:p>","DOI":"10.1145\/2845084","type":"journal-article","created":{"date-parts":[[2016,1,7]],"date-time":"2016-01-07T14:04:54Z","timestamp":1452175494000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["Resistive GP-SIMD Processing-In-Memory"],"prefix":"10.1145","volume":"12","author":[{"given":"Amir","family":"Morad","sequence":"first","affiliation":[{"name":"Technion, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leonid","family":"Yavits","sequence":"additional","affiliation":[{"name":"Technion, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shahar","family":"Kvatinsky","sequence":"additional","affiliation":[{"name":"Technion, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ran","family":"Ginosar","sequence":"additional","affiliation":[{"name":"Technion, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,1,6]]},"reference":[{"volume-title":"Nanotechnology 23","year":"2012","author":"Alibart Fabien","key":"e_1_2_2_1_1"},{"volume-title":"2011 NASA\/ESA Conference on Adaptive Hardware and Systems (AHS). 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