{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:42Z","timestamp":1750306482206,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,2,21]],"date-time":"2016-02-21T00:00:00Z","timestamp":1456012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,2,21]]},"DOI":"10.1145\/2847263.2847266","type":"proceedings-article","created":{"date-parts":[[2016,2,4]],"date-time":"2016-02-04T16:26:02Z","timestamp":1454603162000},"page":"185-194","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths"],"prefix":"10.1145","author":[{"given":"Nachiket","family":"Kapre","sequence":"first","affiliation":[{"name":"Nanyang Technological University, Singapore, Singapore"}]},{"given":"Deheng","family":"Ye","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, Singapore, Singapore"}]}],"member":"320","published-online":{"date-parts":[[2016,2,21]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.32"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145726"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02614-0_10"},{"key":"e_1_3_2_1_4_1","first-page":"1","volume-title":"Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on","author":"Caffarena G.","year":"2012","unstructured":"G. Caffarena and D. Menard . Many-core parallelization of fixed-point optimization of vlsi circuits through gpu devices . In Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on , pages 1 -- 8 , Oct 2012 . G. Caffarena and D. Menard. Many-core parallelization of fixed-point optimization of vlsi circuits through gpu devices. In Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on, pages 1--8, Oct 2012."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.892854"},{"key":"e_1_3_2_1_6_1","first-page":"31","volume-title":"Proceedings of the 2007 GCC Developers? Summit","author":"Callanan S.","year":"2007","unstructured":"S. Callanan , D. J. Dean , and E. Zadok . Extending gcc with modular gimple optimizations . In Proceedings of the 2007 GCC Developers? Summit , pages 31 -- 37 , 2007 . S. Callanan, D. J. Dean, and E. Zadok. Extending gcc with modular gimple optimizations. In Proceedings of the 2007 GCC Developers? Summit, pages 31--37, 2007."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/S0893-9659(01)00107-0"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:NUMA.0000049462.70970.b6"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1656274.1656278"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/0895-7177(89)90202-1"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874889"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.936374"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.873887"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1772954.1772987"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.896306"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/906350"},{"key":"e_1_3_2_1_19_1","unstructured":"J.-P. Merlet. The COPRIN benchmarks. http:\/\/www-sop.inria.fr\/coprin\/logiciels\/ALIAS\/Benches\/benches.html.  J.-P. Merlet. The COPRIN benchmarks. http:\/\/www-sop.inria.fr\/coprin\/logiciels\/ALIAS\/Benches\/benches.html."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","DOI":"10.1137\/1.9780898717716","volume-title":"Introduction to Interval Analysis","author":"Moore R. E.","year":"2009","unstructured":"R. E. Moore , R. B. Kearfott , and M. J. Cloud . Introduction to Interval Analysis . SIAM , 2009 . R. E. Moore, R. B. Kearfott, and M. J. Cloud. Introduction to Interval Analysis. SIAM, 2009."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/367072.367906"},{"key":"e_1_3_2_1_22_1","volume-title":"Int. Conf. on Field Programmable Logic and Applications (FPL)","author":"Osborne W. G.","year":"2007","unstructured":"W. G. Osborne , R. C. C. Cheung , J. Coutinho , W. Luk , and O. Mencer . Automatic accuracy-guaranteed bit-width optimization for fixed and oating-point systems . In Int. Conf. on Field Programmable Logic and Applications (FPL) , 2007 . W. G. Osborne, R. C. C. Cheung, J. Coutinho, W. Luk, and O. Mencer. Automatic accuracy-guaranteed bit-width optimization for fixed and oating-point systems. In Int. Conf. on Field Programmable Logic and Applications (FPL), 2007."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2277978"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650300"}],"event":{"name":"FPGA'16: The 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA'16"},"container-title":["Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847266","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2847263.2847266","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:23Z","timestamp":1750225703000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847266"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2,21]]},"references-count":24,"alternative-id":["10.1145\/2847263.2847266","10.1145\/2847263"],"URL":"https:\/\/doi.org\/10.1145\/2847263.2847266","relation":{},"subject":[],"published":{"date-parts":[[2016,2,21]]},"assertion":[{"value":"2016-02-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}