{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T03:42:00Z","timestamp":1777606920811,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,2,21]],"date-time":"2016-02-21T00:00:00Z","timestamp":1456012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,2,21]]},"DOI":"10.1145\/2847263.2847273","type":"proceedings-article","created":{"date-parts":[[2016,2,4]],"date-time":"2016-02-04T16:26:02Z","timestamp":1454603162000},"page":"254-263","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":41,"title":["FGPU"],"prefix":"10.1145","author":[{"given":"Muhammed","family":"Al Kadi","sequence":"first","affiliation":[{"name":"Ruhr University of Bochum, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benedikt","family":"Janssen","sequence":"additional","affiliation":[{"name":"Ruhr University of Bochum, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Huebner","sequence":"additional","affiliation":[{"name":"Ruhr University of Bochum, Bochum, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,2,21]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Top500 Consortium: The Top 500 supercomputing sites. http:\/\/www.top500.org {Online; accessed 11-Sep-2015}.  Top500 Consortium: The Top 500 supercomputing sites. http:\/\/www.top500.org {Online; accessed 11-Sep-2015}."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412112"},{"key":"e_1_3_2_1_3_1","volume-title":"White Paper","author":"Altera Corporation","year":"2013"},{"key":"e_1_3_2_1_4_1","volume-title":"Reference Guide","author":"Inc.","year":"2012"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718358"},{"key":"e_1_3_2_1_6_1","volume-title":"White Paper","author":"Limited ARM","year":"2014"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2764908"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927456"},{"key":"e_1_3_2_1_9_1","first-page":"1","volume-title":"Field Programmable Logic and Applications (FPL), 2014 24th International Conference on","author":"Jie S. J.","year":"2014"},{"key":"e_1_3_2_1_10_1","unstructured":"Khronos Group. OpenCL 1.2 Specification 2012.  Khronos Group. OpenCL 1.2 Specification 2012."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2010.49"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2012.6416739"},{"key":"e_1_3_2_1_13_1","unstructured":"Mathworks Inc. GPU Programming in MATLAB. Available on mathworks.com\/newsletters {Online; accessed 11-Sep-2015}.  Mathworks Inc. GPU Programming in MATLAB. Available on mathworks.com\/newsletters {Online; accessed 11-Sep-2015}."},{"key":"e_1_3_2_1_14_1","volume-title":"White Paper","author":"Nvidia Corporation","year":"2009"},{"key":"e_1_3_2_1_15_1","unstructured":"Nvidia Corporation. Nvidia Jetson TK1 Development Kit: Bringing GPU-accelerated computing to Embedded Systems (Technical Brief v1.0) 2014.  Nvidia Corporation. Nvidia Jetson TK1 Development Kit: Bringing GPU-accelerated computing to Embedded Systems (Technical Brief v1.0) 2014."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.19"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2014.7082748"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554774"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.55"},{"key":"e_1_3_2_1_21_1","unstructured":"A. Severance and G. Lemieux. Embedded supercomputing in fpgas with the vectorblox mxp matrix processor. In Hardware\/Software Codesign and System Synthesis (CODES   A. Severance and G. Lemieux. Embedded supercomputing in fpgas with the vectorblox mxp matrix processor. In Hardware\/Software Codesign and System Synthesis (CODES"},{"key":"e_1_3_2_1_22_1","first-page":"1","volume-title":"2013 International Conference on","year":"2013"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2013.6567546"},{"key":"e_1_3_2_1_24_1","unstructured":"Xilinx Inc. UltraScale Architecture and Product Overview (v2.2) DS890 2014.  Xilinx Inc. UltraScale Architecture and Product Overview (v2.2) DS890 2014."},{"key":"e_1_3_2_1_25_1","unstructured":"Xilinx Inc. Block Memory Generator v8.2 LogiCORE IP Product Guide (PG058) 2015.  Xilinx Inc. Block Memory Generator v8.2 LogiCORE IP Product Guide (PG058) 2015."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887921"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2160463"}],"event":{"name":"FPGA'16: The 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Monterey California USA","acronym":"FPGA'16","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847273","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2847263.2847273","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:23Z","timestamp":1750225703000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847273"}},"subtitle":["An SIMT-Architecture for FPGAs"],"short-title":[],"issued":{"date-parts":[[2016,2,21]]},"references-count":27,"alternative-id":["10.1145\/2847263.2847273","10.1145\/2847263"],"URL":"https:\/\/doi.org\/10.1145\/2847263.2847273","relation":{},"subject":[],"published":{"date-parts":[[2016,2,21]]},"assertion":[{"value":"2016-02-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}