{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,28]],"date-time":"2026-06-28T03:15:02Z","timestamp":1782616502334,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,2,21]],"date-time":"2016-02-21T00:00:00Z","timestamp":1456012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["1265957"],"award-info":[{"award-number":["1265957"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,2,21]]},"DOI":"10.1145\/2847263.2847278","type":"proceedings-article","created":{"date-parts":[[2016,2,4]],"date-time":"2016-02-04T16:26:02Z","timestamp":1454603162000},"page":"205-214","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":28,"title":["SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing"],"prefix":"10.1145","author":[{"given":"Michael J.","family":"Wirthlin","sequence":"first","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrew M.","family":"Keller","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chase","family":"McCloskey","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Parker","family":"Ridd","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"David","family":"Lee","sequence":"additional","affiliation":[{"name":"Sandia National Laboratories, Albuquerque, NM, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeffrey","family":"Draper","sequence":"additional","affiliation":[{"name":"University of Southern California, Marina del Ray, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2016,2,21]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2006.373294"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/23.658966"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.229"},{"key":"e_1_3_2_1_4_1","volume-title":"Correcting single-event upsets through Virtex partial configuration. Technical report","author":"Carmichael Carl","year":"2000","unstructured":"Carl Carmichael , Michael Caffrey , and Anthony Salazar . Correcting single-event upsets through Virtex partial configuration. Technical report , Xilinx Corporation , June 1, 2000 . XAPP216 (v1.0). Carl Carmichael, Michael Caffrey, and Anthony Salazar. Correcting single-event upsets through Virtex partial configuration. Technical report, Xilinx Corporation, June 1, 2000. XAPP216 (v1.0)."},{"issue":"1","key":"e_1_3_2_1_5_1","first-page":"376","article-title":"Design techniques for Xilinx Virtex FPGA configuration memory scrubbers. Nuclear Science","volume":"60","author":"Herrera-Alzu I.","year":"2013","unstructured":"I. Herrera-Alzu and M. Lopez-Vallejo . Design techniques for Xilinx Virtex FPGA configuration memory scrubbers. Nuclear Science , IEEE Transactions on , 60 ( 1 ): 376 -- 385 , Feb 2013 . I. Herrera-Alzu and M. Lopez-Vallejo. Design techniques for Xilinx Virtex FPGA configuration memory scrubbers. Nuclear Science, IEEE Transactions on, 60(1):376--385, Feb 2013.","journal-title":"IEEE Transactions on"},{"issue":"5","key":"e_1_3_2_1_6_1","first-page":"1545","article-title":"Analysis of the robustness of the TMR architecture in SRAM-based FPGAs. Nuclear Science","volume":"52","author":"Sterpone L.","year":"2005","unstructured":"L. Sterpone and M. Violante . Analysis of the robustness of the TMR architecture in SRAM-based FPGAs. Nuclear Science , IEEE Transactions on , 52 ( 5 ): 1545 -- 1549 , oct. 2005 . L. Sterpone and M. Violante. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs. Nuclear Science, IEEE Transactions on, 52(5):1545--1549, oct. 2005.","journal-title":"IEEE Transactions on"},{"issue":"4","key":"e_1_3_2_1_7_1","first-page":"951","article-title":"Selective protection analysis using a SEU emulator: Testing protocol and case study over the Leon2 processor. Nuclear Science","volume":"54","author":"Aguirre M.A.","year":"2007","unstructured":"M.A. Aguirre , J.N. Tombs , F. Muoz , V. Baena , H. Guzman , J. Napoles , A. Torralba , A. Fernandez-Leon , F. Tortosa-Lopez , and D. Merodio . Selective protection analysis using a SEU emulator: Testing protocol and case study over the Leon2 processor. Nuclear Science , IEEE Transactions on , 54 ( 4 ): 951 -- 956 , Aug 2007 . M.A. Aguirre, J.N. Tombs, F. Muoz, V. Baena, H. Guzman, J. Napoles, A. Torralba, A. Fernandez-Leon, F. Tortosa-Lopez, and D. Merodio. Selective protection analysis using a SEU emulator: Testing protocol and case study over the Leon2 processor. Nuclear Science, IEEE Transactions on, 54(4):951--956, Aug 2007.","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2004.1368020"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2011.5750278"},{"issue":"4","key":"e_1_3_2_1_10_1","first-page":"1992","article-title":"New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors. Nuclear Science","volume":"56","author":"Abate F.","year":"2009","unstructured":"F. Abate , L. Sterpone , C.A. Lisboa , L. Carro , and M. Violante . New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors. Nuclear Science , IEEE Transactions on , 56 ( 4 ): 1992 -- 2000 , Aug 2009 . F. Abate, L. Sterpone, C.A. Lisboa, L. Carro, and M. Violante. New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors. Nuclear Science, IEEE Transactions on, 56(4):1992--2000, Aug 2009.","journal-title":"IEEE Transactions on"},{"issue":"7","key":"e_1_3_2_1_11_1","first-page":"2617","article-title":"A low-cost solution for deploying processor cores in harsh environments. Industrial Electronics","volume":"58","author":"Violante M.","year":"2011","unstructured":"M. Violante , C. Meinhardt , R. Reis , and M.S. Reorda . A low-cost solution for deploying processor cores in harsh environments. Industrial Electronics , IEEE Transactions on , 58 ( 7 ): 2617 -- 2626 , July 2011 . M. Violante, C. Meinhardt, R. Reis, and M.S. Reorda. A low-cost solution for deploying processor cores in harsh environments. Industrial Electronics, IEEE Transactions on, 58(7):2617--2626, July 2011.","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2010.5446663"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/2358952.2359157"},{"key":"e_1_3_2_1_14_1","volume-title":"Military and Aerospace Programmable Logic Devices (MAPLD) Workshop","author":"Miller Gregory","year":"2008","unstructured":"Gregory Miller , Carl Carmichael , and Gary Swift . Mitigation, design flow and troubleshooting a soft processor in a complex FPGA . In Military and Aerospace Programmable Logic Devices (MAPLD) Workshop , 2008 . Gregory Miller, Carl Carmichael, and Gary Swift. Mitigation, design flow and troubleshooting a soft processor in a complex FPGA. In Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 2008."},{"key":"e_1_3_2_1_15_1","volume-title":"Military and Aerospace Programmable Logic Devices (MAPLD) Workshop","author":"Miller Gregory","year":"2009","unstructured":"Gregory Miller , Carl Carmichael , Gary Swift , Mike Pratt , and Gregory R. Allen . Preliminary analysis of a soft-core processor in a Rad Hard by Design Field Programmable Gate Array . In Military and Aerospace Programmable Logic Devices (MAPLD) Workshop , 2009 . Gregory Miller, Carl Carmichael, Gary Swift, Mike Pratt, and Gregory R. Allen. Preliminary analysis of a soft-core processor in a Rad Hard by Design Field Programmable Gate Array. In Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, 2009."},{"key":"e_1_3_2_1_16_1","unstructured":"IEEE standard for a 32-bit microprocessor architecture. IEEE Std 1754--1994 pages 1-- 1995.  IEEE standard for a 32-bit microprocessor architecture. IEEE Std 1754--1994 pages 1-- 1995."},{"key":"e_1_3_2_1_17_1","unstructured":"Aeroflex gaisler LEON3 processor. http:\/\/www.gaisler.com\/index.php\/products\/processors\/leon3.  Aeroflex gaisler LEON3 processor. http:\/\/www.gaisler.com\/index.php\/products\/processors\/leon3."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/CSAE.2012.6272615"},{"key":"e_1_3_2_1_19_1","volume-title":"An evaluation of soft processors as a reliable computing platform. Master's thesis","author":"Gardiner Michael R.","year":"2015","unstructured":"Michael R. Gardiner . An evaluation of soft processors as a reliable computing platform. Master's thesis , Brigham Young University , 2015 . Michael R. Gardiner. An evaluation of soft processors as a reliable computing platform. Master's thesis, Brigham Young University, 2015."},{"key":"e_1_3_2_1_20_1","unstructured":"GRTools. http:\/\/www.gaisler.com\/index.php\/downloads\/grtools.  GRTools. http:\/\/www.gaisler.com\/index.php\/downloads\/grtools."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723154"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2011.5981537"},{"key":"e_1_3_2_1_24_1","volume-title":"The prooceedings of the Military and Aerospace Programmable Logic Devices","author":"Do R.","year":"2011","unstructured":"R. Do . The details of triple modular redundancy: An automated mitigation method of I\/O signals . In The prooceedings of the Military and Aerospace Programmable Logic Devices , 2011 . R. Do. The details of triple modular redundancy: An automated mitigation method of I\/O signals. In The prooceedings of the Military and Aerospace Programmable Logic Devices, 2011."},{"key":"e_1_3_2_1_25_1","unstructured":"BL-TMR and BYU Edif Tools. http:\/\/sourceforge.net\/projects\/byuediftools\/.  BL-TMR and BYU Edif Tools. http:\/\/sourceforge.net\/projects\/byuediftools\/."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2010.5446661"},{"key":"e_1_3_2_1_27_1","volume-title":"November 12","author":"Coproration Xilinx","year":"2014","unstructured":"Xilinx Coproration . 7 Series FPGAs Memory Resources: User Guide. UG473 (v1.11) , November 12 , 2014 . Xilinx Coproration. 7 Series FPGAs Memory Resources: User Guide. UG473 (v1.11), November 12, 2014."},{"key":"e_1_3_2_1_28_1","volume-title":"Swarz. Reliable Computer Systems. A. K. Peters","author":"Daniel","year":"1998","unstructured":"Daniel P. Siewiorek and Robert S . Swarz. Reliable Computer Systems. A. K. Peters , 1998 . Daniel P. Siewiorek and Robert S. Swarz. Reliable Computer Systems. A. K. Peters, 1998."},{"key":"e_1_3_2_1_29_1","volume-title":"Proceedings of the 6th European Conference on Radiation and its Effects on Components and Sysemts (RADECS 2001)","author":"Lima F.","year":"2001","unstructured":"F. Lima , C. Carmichael , J. Fabula , R. Padovani , and R. Reis . A fault injection analysis of Virtex FPGA TMR design methodology . In Proceedings of the 6th European Conference on Radiation and its Effects on Components and Sysemts (RADECS 2001) , 2001 . F. Lima, C. Carmichael, J. Fabula, R. Padovani, and R. Reis. A fault injection analysis of Virtex FPGA TMR design methodology. In Proceedings of the 6th European Conference on Radiation and its Effects on Components and Sysemts (RADECS 2001), 2001."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2005.29"},{"issue":"6","key":"e_1_3_2_1_31_1","first-page":"2150","article-title":"Creme96: A revision of the cosmic ray effects on micro-electronics code. Nuclear Science","volume":"44","author":"Tylka A.J.","year":"1997","unstructured":"A.J. Tylka , J.H. Adams , P.R. Boberg , B. Brownstein , W.F. Dietrich , E.O. Flueckiger , E.L. Petersen , M.A. Shea , D.F. Smart , and E.C. Smith . Creme96: A revision of the cosmic ray effects on micro-electronics code. Nuclear Science , IEEE Transactions on , 44 ( 6 ): 2150 -- 2160 , Dec 1997 . A.J. Tylka, J.H. Adams, P.R. Boberg, B. Brownstein, W.F. Dietrich, E.O. Flueckiger, E.L. Petersen, M.A. Shea, D.F. Smart, and E.C. Smith. Creme96: A revision of the cosmic ray effects on micro-electronics code. Nuclear Science, IEEE Transactions on, 44(6):2150--2160, Dec 1997.","journal-title":"IEEE Transactions on"}],"event":{"name":"FPGA'16: The 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","location":"Monterey California USA","acronym":"FPGA'16","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847278","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2847263.2847278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:23Z","timestamp":1750225703000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847278"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2,21]]},"references-count":30,"alternative-id":["10.1145\/2847263.2847278","10.1145\/2847263"],"URL":"https:\/\/doi.org\/10.1145\/2847263.2847278","relation":{},"subject":[],"published":{"date-parts":[[2016,2,21]]},"assertion":[{"value":"2016-02-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}