{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:43Z","timestamp":1750306483148,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,2,21]],"date-time":"2016-02-21T00:00:00Z","timestamp":1456012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,2,21]]},"DOI":"10.1145\/2847263.2847306","type":"proceedings-article","created":{"date-parts":[[2016,2,4]],"date-time":"2016-02-04T16:26:02Z","timestamp":1454603162000},"page":"284-284","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["t-QuadPlace"],"prefix":"10.1145","author":[{"given":"Nimish","family":"Agashiwala","sequence":"first","affiliation":[{"name":"University of Minnesota Twin Cities, Minneapolis, MN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satya Prakash","family":"Upadhyay","sequence":"additional","affiliation":[{"name":"University of Minnesota Twin Cities, Minneapolis, MN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kia","family":"Bazargan","sequence":"additional","affiliation":[{"name":"University of Minnesota Twin Cities, Minneapolis, MN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,2,21]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/647924.738755"},{"key":"e_1_3_2_1_3_1","volume-title":"Architecture and CAD for deep-submicron FPGAs","author":"Betz Vaughn","year":"2012","unstructured":"Betz , Vaughn , Jonathan Rose , and Alexander Marquardt . Architecture and CAD for deep-submicron FPGAs . Vol. 497 . Springer Science & Business Media , 2012 . Betz, Vaughn, Jonathan Rose, and Alexander Marquardt. Architecture and CAD for deep-submicron FPGAs. Vol. 497. Springer Science & Business Media, 2012."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"e_1_3_2_1_5_1","unstructured":"https:\/\/github.com\/verilog-to-routing\/vtr-verilog-torouting\/blob\/master\/vpr\/VPR User Manual 7.0.pdf  https:\/\/github.com\/verilog-to-routing\/vtr-verilog-torouting\/blob\/master\/vpr\/VPR User Manual 7.0.pdf"},{"key":"e_1_3_2_1_6_1","volume-title":"Logic synthesis and optimization benchmarks user guide: version 3.0","author":"Yang Saeyang","year":"1991","unstructured":"Yang , Saeyang . Logic synthesis and optimization benchmarks user guide: version 3.0 . Microelectronics Center of North Carolina (MCNC) , 1991 . Yang, Saeyang. Logic synthesis and optimization benchmarks user guide: version 3.0. Microelectronics Center of North Carolina (MCNC), 1991."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"Pan David Z. Bill Halpin and Haoxing Ren. Timing-driven placement. Handbook of Algorithms for VLSI Physical Automation (2007): 223--233.  Pan David Z. Bill Halpin and Haoxing Ren. Timing-driven placement. Handbook of Algorithms for VLSI Physical Automation (2007): 223--233.","DOI":"10.1201\/9781420013481.ch21"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.521529"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/800033.800787"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/317825.317845"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774597"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846367"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640016"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379065"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009930"},{"key":"e_1_3_2_1_16_1","volume-title":"RITUAL: A performance driven placement algorithm. Circuits and Systems II: Analog and Digital Signal Processing","author":"Srinivasan Arvind","year":"1992","unstructured":"Srinivasan , Arvind , Kamal Chaudhary , and Ernest S. Kuh . RITUAL: A performance driven placement algorithm. Circuits and Systems II: Analog and Digital Signal Processing , IEEE Transactions on 39.11 ( 1992 ): 825--840. Srinivasan, Arvind, Kamal Chaudhary, and Ernest S. Kuh. RITUAL: A performance driven placement algorithm. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on 39.11 (1992): 825--840."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.842812"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.67789"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775888"},{"key":"e_1_3_2_1_20_1","volume-title":"Field Programmable Logic and Applications, 2005. International Conference on. IEEE","author":"Xu Yonghong","year":"2005","unstructured":"Xu , Yonghong , and Mohammed AS Khalid . QPF : efficient quadratic placement for FPGAs . Field Programmable Logic and Applications, 2005. International Conference on. IEEE , 2005 . Xu, Yonghong, and Mohammed AS Khalid. QPF: efficient quadratic placement for FPGAs. Field Programmable Logic and Applications, 2005. International Conference on. IEEE, 2005."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/1975015.1975357"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339278"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170567"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488746"}],"event":{"name":"FPGA'16: The 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey California USA","acronym":"FPGA'16"},"container-title":["Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847306","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:24Z","timestamp":1750225704000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2847263.2847306"}},"subtitle":["Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only)"],"short-title":[],"issued":{"date-parts":[[2016,2,21]]},"references-count":24,"alternative-id":["10.1145\/2847263.2847306","10.1145\/2847263"],"URL":"https:\/\/doi.org\/10.1145\/2847263.2847306","relation":{},"subject":[],"published":{"date-parts":[[2016,2,21]]},"assertion":[{"value":"2016-02-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}