{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:58Z","timestamp":1750306318415,"version":"3.41.0"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2016,5,11]],"date-time":"2016-05-11T00:00:00Z","timestamp":1462924800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Korean government","award":["2015R1A2A2A01008037"],"award-info":[{"award-number":["2015R1A2A2A01008037"]}]},{"name":"2015 Research Fund","award":["1.150121.01"],"award-info":[{"award-number":["1.150121.01"]}]},{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100002613","name":"UNIST","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100002613","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2016,7,26]]},"abstract":"<jats:p>A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock frequency. Some cells that are particularly slow in NTV mode are optimized through transistor sizing and stack removal; static noise margin of each gate is extracted and appended in a library so that function failures can be checked and removed during synthesis. A new gate-sizing algorithm is proposed that takes account of timing slacks at both modes. A new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock-tree synthesis is reformulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock-path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV mode clock period is reduced by 24%, on average; clock skew at NTV decreases by 13%, on average; and NTV mode energy-delay product is reduced by 20%, on average.<\/jats:p>","DOI":"10.1145\/2856032","type":"journal-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T14:30:58Z","timestamp":1463149858000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization"],"prefix":"10.1145","volume":"21","author":[{"given":"Sangmin","family":"Kim","sequence":"first","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seokhyeong","family":"Kang","sequence":"additional","affiliation":[{"name":"UNIST, Ulsan, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[{"name":"KAIST, Daejeon, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,5,11]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Retrieved","author":"Berkeley Logic Synthesis and Verification Group","year":"2014","unstructured":"Berkeley Logic Synthesis and Verification Group . 2014 . ABC: a system for sequential synthesis and verification . Retrieved March 25, 2016 from http:\/\/www.eecs.berkeley.edu\/&sim;alanmi\/abc\/. Release 140728. Berkeley Logic Synthesis and Verification Group. 2014. ABC: a system for sequential synthesis and verification. Retrieved March 25, 2016 from http:\/\/www.eecs.berkeley.edu\/&sim;alanmi\/abc\/. Release 140728."},{"key":"e_1_2_1_2_1","unstructured":"R. Deokar and V. Patwardhan. 2015. How to Achieve Optimal PPA and Up to 10X TAT Gain in Your Next Digital Design Implementation. White paper. Cadence Design Systems. San Jose.  R. Deokar and V. Patwardhan. 2015. How to Achieve Optimal PPA and Up to 10X TAT Gain in Your Next Digital Design Implementation. White paper. Cadence Design Systems. San Jose."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837421"},{"key":"e_1_2_1_4_1","unstructured":"Gurobi Optimization Inc. 2015. Gurobi Optimizer Reference Manual. Gurobi Optimization. Houston.  Gurobi Optimization Inc. 2015. Gurobi Optimizer Reference Manual. Gurobi Optimization. Houston."},{"volume-title":"Proceedings of the IEEE Symposium on Low Power Electronics. 8--11","author":"Horowitz M.","key":"e_1_2_1_5_1","unstructured":"M. Horowitz , T. Indermaur , and R. Gonzalez . 1994. Low-power digital design . In Proceedings of the IEEE Symposium on Low Power Electronics. 8--11 . M. Horowitz, T. Indermaur, and R. Gonzalez. 1994. Low-power digital design. In Proceedings of the IEEE Symposium on Low Power Electronics. 8--11."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169689"},{"volume-title":"Retrieved","year":"1989","key":"e_1_2_1_7_1","unstructured":"ISCAS89. 1989 . ISCAS\u201989 benchmark home page . Retrieved March 25, 2016 from http:\/\/www.cbl.ncsu.edu\/ benchmarks\/ISCAS89\/. ISCAS89. 1989. ISCAS\u201989 benchmark home page. Retrieved March 25, 2016 from http:\/\/www.cbl.ncsu.edu\/ benchmarks\/ISCAS89\/."},{"volume-title":"Retrieved","year":"1999","key":"e_1_2_1_8_1","unstructured":"ITC99. 1999 . ITC\u201999 benchmark home page . Retrieved March 25, 2016 from http:\/\/cerc.utexas.edu\/ itc99-benchmarks\/bench.html. ITC99. 1999. ITC\u201999 benchmark home page. Retrieved March 25, 2016 from http:\/\/cerc.utexas.edu\/ itc99-benchmarks\/bench.html."},{"volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference. 66--68","author":"Jain S.","key":"e_1_2_1_9_1","unstructured":"S. Jain , S. Khare , S. Yada , V. Ambili , P. Salihundam , S. Ramani , S. Muthukumar , M. Srinivasan , A. Kumar , S. Gb , R. Ramanarayanan , V. Erraguntla , J. Howard , S. Vangal , S. Dighe , G. Ruhl , P. Aseron , H. Wilson , N. Borkar , V. De , and S. Borkar . 2012. A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS . In Proceedings of the IEEE International Solid-State Circuits Conference. 66--68 . S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, M. Srinivasan, A. Kumar, S. Gb, R. Ramanarayanan, V. Erraguntla, J. Howard, S. Vangal, S. Dighe, G. Ruhl, P. Aseron, H. Wilson, N. Borkar, V. De, and S. Borkar. 2012. A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference. 66--68."},{"volume-title":"Proceedings of the IEEE Subthreshold Microelectronics Conference. 16--18","author":"Karlsson A.","key":"e_1_2_1_10_1","unstructured":"A. Karlsson , O. Andersson , J. Sparso , and J. Rodrigues . 2012. IR-drop reduction in sub-VT circuits by de-synchronization . In Proceedings of the IEEE Subthreshold Microelectronics Conference. 16--18 . A. Karlsson, O. Andersson, J. Sparso, and J. Rodrigues. 2012. IR-drop reduction in sub-VT circuits by de-synchronization. In Proceedings of the IEEE Subthreshold Microelectronics Conference. 16--18."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228572"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228533"},{"volume-title":"Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation. 251--256","author":"Manuzzato A.","key":"e_1_2_1_13_1","unstructured":"A. Manuzzato , F. Campi , V. Liberali , and D. Pandini . 2013. Design methodology for low-power embedded microprocessors . In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation. 251--256 . A. Manuzzato, F. Campi, V. Liberali, and D. Pandini. 2013. Design methodology for low-power embedded microprocessors. In Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation. 251--256."},{"key":"e_1_2_1_14_1","first-page":"299","article-title":"Large-step Markov chains for the traveling salesman problem","volume":"5","author":"Martin O.","year":"1991","unstructured":"O. Martin , S. Otto , and E. Felten . 1991 . Large-step Markov chains for the traveling salesman problem . Complex Systems 5 , 299 -- 326 . O. Martin, S. Otto, and E. Felten. 1991. Large-step Markov chains for the traveling salesman problem. Complex Systems 5, 299--326.","journal-title":"Complex Systems"},{"key":"e_1_2_1_15_1","unstructured":"Mentor Graphics. 2013. Multi-Voltage Design Flow with Olympus-SoC. White paper. Mentor Graphics. Wilsonville.  Mentor Graphics. 2013. Multi-Voltage Design Flow with Olympus-SoC. White paper. Mentor Graphics. Wilsonville."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344601"},{"volume-title":"Retrieved","year":"2009","key":"e_1_2_1_17_1","unstructured":"OpenCores. 2009 . Opencores . Retrieved March 25, 2016 from http:\/\/www.opencores.org\/. OpenCores. 2009. Opencores. Retrieved March 25, 2016 from http:\/\/www.opencores.org\/."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013266"},{"key":"e_1_2_1_19_1","first-page":"1","article-title":"Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling","volume":"312","author":"Pu Y.","year":"2014","unstructured":"Y. Pu , J. Echeverri , M. Meijer , and J. Gyvez . 2014 . Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling . In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 312 : 1 -- 312 :2. Y. Pu, J. Echeverri, M. Meijer, and J. Gyvez. 2014. Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 312:1--312:2.","journal-title":"Proceedings of the Design, Automation and Test in Europe Conference and Exhibition."},{"key":"e_1_2_1_20_1","unstructured":"C. Roth and L. Kinney. 2009. Fundamentals of Logic Design. Cengage Learning. Stamford.  C. Roth and L. Kinney. 2009. Fundamentals of Logic Design. Cengage Learning. Stamford."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840862"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061654"},{"key":"e_1_2_1_23_1","unstructured":"Synopsys. 2013a. CustomSim User Guide. Synopsys. Mountain View.  Synopsys. 2013a. CustomSim User Guide. Synopsys. Mountain View."},{"key":"e_1_2_1_24_1","unstructured":"Synopsys. 2013b. Design Compiler User Guide. Synopsys. Mountain View.  Synopsys. 2013b. Design Compiler User Guide. Synopsys. Mountain View."},{"key":"e_1_2_1_25_1","unstructured":"Synopsys. 2013c. IC Compiler User Guide. Synopsys. Mountain View.  Synopsys. 2013c. IC Compiler User Guide. Synopsys. Mountain View."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2856032","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2856032","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:54:11Z","timestamp":1750222451000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2856032"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,11]]},"references-count":25,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2016,7,26]]}},"alternative-id":["10.1145\/2856032"],"URL":"https:\/\/doi.org\/10.1145\/2856032","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2016,5,11]]},"assertion":[{"value":"2015-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-05-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}