{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:18:00Z","timestamp":1763468280465,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2015,12,8]],"date-time":"2015-12-08T00:00:00Z","timestamp":1449532800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[2015,12,8]]},"abstract":"<jats:p>Customized architecture is widely recognized as an important approach for improved performance and energyefficiency. To balance generality and customization benefit, researchers have proposed to federate heterogeneous micro-engines. Using the 10x10 architecture and an integrated image and vision benchmark as a case study, we explore the performance and energy benefits achievable. Results for current 32nm technology and DDR3 memory show 10x10 architecture benefits of 140x performance and 72x energy overall. Adding 3D-stacked DRAM increase benefits to 171x (performance) and 100x (energy). Finally, considering future 7nm transistor process, benefits as large as 597x (performance) and 137x energy are observed.<\/jats:p>","DOI":"10.1145\/2856113.2856115","type":"journal-article","created":{"date-parts":[[2015,12,10]],"date-time":"2015-12-10T14:22:10Z","timestamp":1449757330000},"page":"2-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["10x10"],"prefix":"10.1145","volume":"43","author":[{"given":"Andrew A.","family":"Chien","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tung","family":"Thanh-Hoang","sequence":"additional","affiliation":[{"name":"University of Chicago, Chicago, Illinois"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dilip","family":"Vasudevan","sequence":"additional","affiliation":[{"name":"University of Chicago, Chicago, Illinois"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuanwei","family":"Fang","sequence":"additional","affiliation":[{"name":"University of Chicago, Chicago, Illinois"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amirali","family":"Shambayati","sequence":"additional","affiliation":[{"name":"University of Chicago, Chicago, Illinois"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2007.4785543"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"e_1_2_1_4_1","first-page":"1987","volume-title":"10x10: A general-purpose architectural approach to heterogeneity and energy efficiency","author":"Chien A. A.","year":"2011","unstructured":"A. A. Chien , A. Snavely , and M. Gahagan , \" 10x10: A general-purpose architectural approach to heterogeneity and energy efficiency ,\" vol. 4 , pp. 1987 -- 1996 , 2011 . A. A. Chien, A. Snavely, and M. Gahagan, \"10x10: A general-purpose architectural approach to heterogeneity and energy efficiency,\" vol. 4, pp. 1987--1996, 2011."},{"key":"e_1_2_1_5_1","unstructured":"Pacific Northwest National Laboratory (PNNL) \"PERFECT benchmark.\" Online http:\/\/hpc.pnl.gov\/ PERFECT\/.  Pacific Northwest National Laboratory (PNNL) \"PERFECT benchmark.\" Online http:\/\/hpc.pnl.gov\/ PERFECT\/."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2490302.2490307"},{"key":"e_1_2_1_7_1","unstructured":"Synopsys \"Processor Designer.\" Online http:\/\/www. synopsys.com\/IP\/ProcessorIP.  Synopsys \"Processor Designer.\" Online http:\/\/www. synopsys.com\/IP\/ProcessorIP."},{"key":"e_1_2_1_8_1","volume-title":"BnB: Bit-nibble-Byte microengine for accelerating low-level bit operations,\" in Proc. of the Great Lakes Symp. on VLSI (GSVLSI)","author":"Andrew D.","year":"2015","unstructured":"D. V. and A. C. Andrew , \" BnB: Bit-nibble-Byte microengine for accelerating low-level bit operations,\" in Proc. of the Great Lakes Symp. on VLSI (GSVLSI) , 2015 . D. V. and A. C. Andrew, \"BnB: Bit-nibble-Byte microengine for accelerating low-level bit operations,\" in Proc. of the Great Lakes Symp. on VLSI (GSVLSI), 2015."},{"key":"e_1_2_1_9_1","first-page":"1","article-title":"Performance and energy limits of a processor-integrated fft accelerator","author":"Tung H. T.","year":"2014","unstructured":"H. T. Tung , A. Shambayati , C. Deutschbein , H. Hoffmann , and A. Chien , \" Performance and energy limits of a processor-integrated fft accelerator ,\" in Proc. of the IEEE High Performance Extreme Computing Conf. (HPEC) , pp. 1 -- 6 , 2014 . H. T. Tung, A. Shambayati, C. Deutschbein, H. Hoffmann, and A. Chien, \"Performance and energy limits of a processor-integrated fft accelerator,\" in Proc. of the IEEE High Performance Extreme Computing Conf. (HPEC), pp. 1--6, 2014.","journal-title":"Proc. of the IEEE High Performance Extreme Computing Conf. (HPEC)"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2159542.2159547"},{"key":"e_1_2_1_11_1","volume-title":"Architectures and Processors (ASAP)","author":"Tung H. T.","year":"2015","unstructured":"H. T. Tung , A. Shambayati , F. Yuanwei , H. Hoffmann , and A. A. Chien , \" Does arithmetic logic dominate data movement ? A systematic comparison of energyefficiency for fft accelerators,\" in Proc. of the IEEE Application-specific Systems , Architectures and Processors (ASAP) , 2015 H. T. Tung, A. Shambayati, F. Yuanwei, H. Hoffmann, and A. A. Chien, \"Does arithmetic logic dominate data movement ? A systematic comparison of energyefficiency for fft accelerators,\" in Proc. of the IEEE Application-specific Systems, Architectures and Processors (ASAP), 2015"},{"key":"e_1_2_1_12_1","volume-title":"Automation and Test in Europe (DATE)","author":"Tung H. T.","year":"2016","unstructured":"H. T. Tung , A. Shambayati , , and A. A. Chien , \" A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in acceleratorcentric heterogeneous systems,\" in Proc. of Design , Automation and Test in Europe (DATE) , 2016 (to appear). H. T. Tung, A. Shambayati, , and A. A. Chien, \"A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in acceleratorcentric heterogeneous systems,\" in Proc. of Design, Automation and Test in Europe (DATE), 2016 (to appear)."},{"key":"e_1_2_1_13_1","volume-title":"Generalized pattern matching micro-engine,\" in Workshop on Architectures and Systems for Big Data (joined with ISCA)","author":"Yuanwei F.","year":"2014","unstructured":"F. Yuanwei , R. Raihan , V. Dilip , and A. A. Chien , \" Generalized pattern matching micro-engine,\" in Workshop on Architectures and Systems for Big Data (joined with ISCA) , 2014 . F. Yuanwei, R. Raihan, V. Dilip, and A. A. Chien, \"Generalized pattern matching micro-engine,\" in Workshop on Architectures and Systems for Big Data (joined with ISCA), 2014."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_2_1_15_1","volume-title":"HP Lab.","author":"Muralimanohar N.","year":"2009","unstructured":"N. Muralimanohar , R. Balasubramonian , and N. P. Jouppi , \" Cacti 6.0: A tool to model large caches,\" in Technical report , HP Lab. , 2009 . N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, \"Cacti 6.0: A tool to model large caches,\" in Technical report, HP Lab., 2009."},{"key":"e_1_2_1_16_1","volume-title":"7nm FinFET cell library.\" Download http:\/\/sportlab.usc.edu\/downloads","author":"USC-SPORT","year":"2014","unstructured":"USC-SPORT , \"PERFECT : 7nm FinFET cell library.\" Download http:\/\/sportlab.usc.edu\/downloads , 2014 . USC-SPORT, \"PERFECT: 7nm FinFET cell library.\" Download http:\/\/sportlab.usc.edu\/downloads, 2014."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_2_1_18_1","volume-title":"spec. v1.1","author":"HMC-Consortium","year":"2014","unstructured":"HMC-Consortium , \" Hybrid Memory Cube , spec. v1.1 ,\" 2014 . HMC-Consortium, \"Hybrid Memory Cube, spec. v1.1,\" 2014."},{"key":"e_1_2_1_19_1","first-page":"33","volume-title":"Automation and Test in Europe (DATE)","author":"Chen K.","year":"2012","unstructured":"K. Chen , S. Li , N. Muralimanohar , J. H. Ahn , J. Brockman , and N. Jouppi , \" Cacti-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory,\" in Proc. of the Design , Automation and Test in Europe (DATE) , pp. 33 -- 38 , Mar 2012 . K. Chen, S. Li, N. Muralimanohar, J. H. Ahn, J. Brockman, and N. Jouppi, \"Cacti-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory,\" in Proc. of the Design, Automation and Test in Europe (DATE), pp. 33--38, Mar 2012."},{"key":"e_1_2_1_20_1","volume-title":"Department of Computer Science","author":"Guha A.","year":"2013","unstructured":"A. Guha , Y. Zhang , R. ur Rasool, and A. A. Chien, \"Calibrating the relationship between hardware customization and energy efficiency,\" in Technical report , Department of Computer Science , University of Chicago , July 2013 . A. Guha, Y. Zhang, R. ur Rasool, and A. A. Chien, \"Calibrating the relationship between hardware customization and energy efficiency,\" in Technical report, Department of Computer Science, University of Chicago, July 2013."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2010.2059721"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.51"},{"key":"e_1_2_1_24_1","volume-title":"Myriad 2: Eye of the computational vision storm,\" in Proc. of Hot Chips","author":"David M.","year":"2014","unstructured":"M. David , B. Brendan , R. Richard , C. Fergal , B. Cormac , and D. David , \" Myriad 2: Eye of the computational vision storm,\" in Proc. of Hot Chips , 2014 . M. David, B. Brendan, R. Richard, C. Fergal, B. Cormac, and D. David, \"Myriad 2: Eye of the computational vision storm,\" in Proc. of Hot Chips, 2014."},{"key":"e_1_2_1_25_1","first-page":"1","volume-title":"Symp. on High Performance Computer Architecture (HPCA)","author":"Chandramoorthy N.","year":"2015","unstructured":"N. Chandramoorthy , G. Tagliavini , K. Irick , A. Pullini , S. Advani , S. Al Habsi , M. Cotter , J. Sampson , V. Narayanan , and L. Benini , \" Exploring architectural heterogeneity in intelligent vision systems,\" in Proc. of the Int . Symp. on High Performance Computer Architecture (HPCA) , pp. 1 -- 12 , Feb. 2015 . N. Chandramoorthy, G. Tagliavini, K. Irick, A. Pullini, S. Advani, S. Al Habsi, M. Cotter, J. Sampson, V. Narayanan, and L. Benini, \"Exploring architectural heterogeneity in intelligent vision systems,\" in Proc. of the Int. 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