{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,25]],"date-time":"2025-07-25T10:38:08Z","timestamp":1753439888894,"version":"3.41.0"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2016,4,21]],"date-time":"2016-04-21T00:00:00Z","timestamp":1461196800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European Research Council Advanced","award":["DAL 267175"],"award-info":[{"award-number":["DAL 267175"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Comput. Syst."],"published-print":{"date-parts":[[2016,5,5]]},"abstract":"<jats:p>Recent work in the field of value prediction (VP) has shown that given an efficient confidence estimation mechanism, prediction validation could be removed from the out-of-order engine and delayed until commit time. As a result, a simple recovery mechanism\u2014pipeline squashing\u2014can be used, whereas the out-of-order engine remains mostly unmodified.<\/jats:p>\n          <jats:p>Yet, VP and validation at commit time require additional ports on the physical register file, potentially rendering the overall number of ports unbearable. Fortunately, VP also implies that many single-cycle ALU instructions have their operands predicted in the front-end and can be executed in-place, in-order. Similarly, the execution of single-cycle instructions whose result has been predicted can be delayed until commit time since predictions are validated at commit time.<\/jats:p>\n          <jats:p>Consequently, a significant number of instructions\u201410% to 70% in our experiments\u2014can bypass the out-of-order engine, allowing for a reduction of the issue width. This reduction paves the way for a truly practical implementation of VP. Furthermore, since VP in itself usually increases performance, our resulting {Early\u2014Out-of-Order\u2014Late} Execution architecture, EOLE, is often more efficient than a baseline VP-augmented 6-issue superscalar while having a significantly narrower 4-issue out-of-order engine.<\/jats:p>","DOI":"10.1145\/2870632","type":"journal-article","created":{"date-parts":[[2016,4,22]],"date-time":"2016-04-22T13:53:06Z","timestamp":1461333186000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["EOLE"],"prefix":"10.1145","volume":"34","author":[{"given":"Arthur","family":"Perais","sequence":"first","affiliation":[{"name":"INRIA"}]},{"given":"Andr\u00e9","family":"Seznec","sequence":"additional","affiliation":[{"name":"INRIA"}]}],"member":"320","published-online":{"date-parts":[[2016,4,21]]},"reference":[{"volume-title":"Proceedings of the International Symposium on Microarchitecture.","author":"Ahuja P. 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