{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:18:12Z","timestamp":1763468292627,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2016,2,26]],"date-time":"2016-02-26T00:00:00Z","timestamp":1456444800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2016,6,7]]},"abstract":"<jats:p>Model-based hardware design allows one to map a single model to multiple hardware and\/or software architectures, essentially eliminating one of the major limitations of manual coding in C or RTL. Model-based design for hardware implementation has traditionally offered a limited set of microarchitectures, which are typically suitable only for some application scenarios. In this article we illustrate how digital signal processing (DSP) algorithms can be modeled as flexible intellectual property blocks to be used within the popular Simulink model-based design environment. These blocks are written in C and are designed for both functional simulation and hardware implementation, including architectural design space exploration and hardware implementation through high-level synthesis. A key advantage of our modeling approach is that the very same bit-accurate model is used for simulation and high-level synthesis. To prove the feasibility of our proposed approach, we modeled a fast Fourier transform (FFT) algorithm and synthesized it for different DSP applications with very different performance and cost requirements. We also implemented a high-level-synthesis (HLS) intellectual property (IP) generator that can generate flexible FFT HLS-IP blocks that can be mapped to multiple micro-\/macroarchitectures, to enable design space exploration as well as being used for functional simulation in the Simulink environment.<\/jats:p>","DOI":"10.1145\/2871737","type":"journal-article","created":{"date-parts":[[2016,2,29]],"date-time":"2016-02-29T15:09:04Z","timestamp":1456758544000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis"],"prefix":"10.1145","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9747-221X","authenticated-orcid":false,"given":"Shahzad Ahmad","family":"Butt","sequence":"first","affiliation":[{"name":"National University of Computer and Emerging Sciences Lahore, Lahore, Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehdi","family":"Roozmeh","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luciano","family":"Lavagno","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,2,26]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"FFT LogiCORE - xilinx FFT IP generator. Retrieved from http:\/\/www.xilinx.com\/products\/intellectual- property\/.  FFT LogiCORE - xilinx FFT IP generator. Retrieved from http:\/\/www.xilinx.com\/products\/intellectual- property\/."},{"key":"e_1_2_1_2_1","unstructured":"FFT MegaCore function - FFT megacore\u00ae function: A high-performance highly parameterizable FFT processor. Retrieved from http:\/\/www.altera.com\/products\/ip\/dsp\/transforms\/m-ham-fft.html.  FFT MegaCore function - FFT megacore\u00ae function: A high-performance highly parameterizable FFT processor. Retrieved from http:\/\/www.altera.com\/products\/ip\/dsp\/transforms\/m-ham-fft.html."},{"key":"e_1_2_1_3_1","unstructured":"LabVIEW system design software. Retrieved from http:\/\/www.ni.com\/labview\/.  LabVIEW system design software. Retrieved from http:\/\/www.ni.com\/labview\/."},{"volume-title":"workshop: Generates C\/C++ from simulink models.","key":"e_1_2_1_4_1"},{"key":"e_1_2_1_5_1","unstructured":"Simulink - Simulink is a block diagram environment for multidomain simulation and model-based design. Retrieved from http:\/\/www.mathworks.com\/products\/simulink.  Simulink - Simulink is a block diagram environment for multidomain simulation and model-based design. Retrieved from http:\/\/www.mathworks.com\/products\/simulink."},{"key":"e_1_2_1_6_1","unstructured":"Simulink HDL coder - generate HDL code from simulink models and MATLAB code. Retrieved from http:\/\/www.mathworks.com\/products\/slhdlcoder.  Simulink HDL coder - generate HDL code from simulink models and MATLAB code. Retrieved from http:\/\/www.mathworks.com\/products\/slhdlcoder."},{"key":"e_1_2_1_7_1","unstructured":"Synphony model compiler. Retrieved from http:\/\/www.synopsys.com\/Tools\/Implementation\/FPGAImplementation\/Pages\/synphony-model-compiler.aspx.  Synphony model compiler. Retrieved from http:\/\/www.synopsys.com\/Tools\/Implementation\/FPGAImplementation\/Pages\/synphony-model-compiler.aspx."},{"volume-title":"Proceedings of the Design and Test Symposium (IDT\u201912)","author":"Butt S. A.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/SIECPC.2011.5876891"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380445.2380493"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1117\/1.JEI.23.5.053012"},{"volume-title":"Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems. 97--100","year":"2009","author":"Chouliaras V.","key":"e_1_2_1_12_1"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/3041403.3041420"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391616"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278491"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2008.4517884"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/334012.334015"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1143549.1143728"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1143549.1143728"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1999.832429"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSSTA.2008.13"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the 24th International Conference on Microelectronics, 2004","volume":"2","author":"Murphy G.","year":"2004"},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"Goran Nikolic. April 2011. Fourier Transforms\u2014Approach to Scientific Principles. Intech Open.  Goran Nikolic. April 2011. Fourier Transforms\u2014Approach to Scientific Principles. Intech Open.","DOI":"10.5772\/650"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/AEECT.2011.6132515"},{"volume-title":"Proceedings of the 29th Symposium on Information Theory in the Benelux. WIC organisation","author":"Shao Xiaoying","key":"e_1_2_1_25_1"},{"key":"e_1_2_1_26_1","unstructured":"Andres Takach. 2010. Creating C++ IP for high performance hardware implementation of FFTs. In DesignCon2002.  Andres Takach. 2010. Creating C++ IP for high performance hardware implementation of FFTs. In DesignCon2002."},{"volume-title":"Proceedings of the IEEE Mediterranean Electrotechnical Conference, 2006","year":"2006","author":"Toledo A.","key":"e_1_2_1_27_1"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755951.1755906"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2871737","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2871737","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:39:16Z","timestamp":1750221556000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2871737"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2,26]]},"references-count":28,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2016,6,7]]}},"alternative-id":["10.1145\/2871737"],"URL":"https:\/\/doi.org\/10.1145\/2871737","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2016,2,26]]},"assertion":[{"value":"2015-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-10-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-02-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}