{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:46:50Z","timestamp":1772164010296,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":53,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T00:00:00Z","timestamp":1490400000000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1012759, CNS-1116237, and CCF-1536795"],"award-info":[{"award-number":["CCF-1012759, CNS-1116237, and CCF-1536795"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003030","name":"Ag\u00e8ncia de Gesti\u00f3 d'Ajuts Universitaris i de Recerca","doi-asserted-by":"publisher","award":["2014SGR-1427"],"award-info":[{"award-number":["2014SGR-1427"]}],"id":[{"id":"10.13039\/501100003030","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"publisher","award":["PCIN-2015-012"],"award-info":[{"award-number":["PCIN-2015-012"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,3,25]]},"DOI":"10.1145\/2872362.2872396","type":"proceedings-article","created":{"date-parts":[[2016,3,28]],"date-time":"2016-03-28T09:24:30Z","timestamp":1459157070000},"page":"3-17","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":18,"title":["WiSync"],"prefix":"10.1145","author":[{"given":"Sergi","family":"Abadal","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign &amp; Universitat Politecnica de Catalunya, Urbana, IL, USA"}]},{"given":"Albert","family":"Cabellos-Aparicio","sequence":"additional","affiliation":[{"name":"Universitat Politecnica de Catalunya, Barcelona, Spain"}]},{"given":"Eduard","family":"Alarcon","sequence":"additional","affiliation":[{"name":"Universitat Politecnica de Catalunya, Barcelona, Spain"}]},{"given":"Josep","family":"Torrellas","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL, USA"}]}],"member":"320","published-online":{"date-parts":[[2016,3,25]]},"reference":[{"issue":"11","key":"e_1_3_2_1_1_1","first-page":"137","volume":"51","author":"Abadal S.","year":"2013","unstructured":"S. Abadal, E. Alarcon, M. C. Lemme, M. Nemirovsky, and A. Cabellos-Aparicio. Graphene-enabled Wireless Communication for Massive Multicore Architectures. IEEE Communications Magazine, 51(11):137--143, 2013.","journal-title":"Graphene-enabled Wireless Communication for Massive Multicore Architectures. IEEE Communications Magazine"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2015.2487098"},{"issue":"5","key":"e_1_3_2_1_3_1","first-page":"52","volume":"35","author":"Abadal S.","year":"2015","unstructured":"S. Abadal, B. Sheinman, O. Katz, O. Markish, D. Elad, Y. Fournier, D. Roca, M. Hanzich, G. Houzeaux, M. Nemirovsky, E. Alarcon, and A. Cabellos-Aparicio. Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach. IEEE MICRO, 35(5):52--61, 2015.","journal-title":"Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach. IEEE MICRO"},{"key":"e_1_3_2_1_4_1","first-page":"893","volume-title":"Proceedings of the IEEE International Parallel and Distributed Processing Symposium","author":"Abellan J. L.","year":"2011","unstructured":"J. L. Abellan, J. Fernandez, and M. E. Acacio. GLocks: Efficient Support for Highly-contended Locks in Many-core CMPs. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium, pages 893--905, May 2011."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2011.304"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193932"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/SUPERC.1990.130019"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/554432"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337178"},{"key":"e_1_3_2_1_11_1","first-page":"191","volume-title":"Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. In Proceedings of the 14th International Symposium on High Performance Computer Architecture","author":"Chang M. F.","year":"2008","unstructured":"M. F. Chang, J. Cong, A. Kaplan, M. Naik, G. Reinman, E. Socher, and S.-W. Tam. CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect. In Proceedings of the 14th International Symposium on High Performance Computer Architecture, pages 191--202, February 2008."},{"key":"e_1_3_2_1_12_1","volume-title":"CRAY T3D System Architecture Overview","author":"Cray Research Inc.","year":"1993","unstructured":"Cray Research Inc. CRAY T3D System Architecture Overview, 1993."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193835"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.224"},{"key":"e_1_3_2_1_15_1","author":"Gara A.","year":"2005","unstructured":"A. Gara, M. A. Blumrich, D. Chen, G. L.-T. Chiu, P. Coteus, M. E. Giampapa, R. A. Haring, P. Heidelberger, D. Hoenicke, G. V. Kopcsay, T. A. Liebsch, M. Ohmacht, B. D. Steinmacher-Burow, T. Takken, and P. Vranas. Overview of the Blue Gene\/L System Architecture. In IBM Journal of Research and Development, March\/May 2005.","journal-title":"Overview of the Blue Gene\/L System Architecture. In IBM Journal of Research and Development"},{"key":"e_1_3_2_1_16_1","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy J. L.","year":"2012","unstructured":"J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach, Fifth Edition. Morgan Kaufmann, 2012."},{"key":"e_1_3_2_1_17_1","volume-title":"Intel Products. ark.intel.com","author":"Intel Corporation","year":"2015","unstructured":"Intel Corporation. Intel Products. ark.intel.com, 2015."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703431"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674771"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TTHZ.2012.2236836"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.28"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155630"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854332"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2379640"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264206"},{"key":"e_1_3_2_1_26_1","first-page":"414","volume-title":"Milos Prvulovic. MiSAR: Minimalistic Synchronization Accelerator with Resource Overflow Management. In Proceedings of the 42nd Annual International Symposium on Computer Architecture","author":"Liang C.-K.","year":"2015","unstructured":"C.-K. Liang and Milos Prvulovic. MiSAR: Minimalistic Synchronization Accelerator with Resource Overflow Management. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, pages 414--426, June 2015."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195490"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2786572.2789983"},{"key":"e_1_3_2_1_29_1","volume-title":"Wireless Channel, and Devices","author":"Matolak D.","year":"2012","unstructured":"D. Matolak, A. Kodi, S. Kaya, D. DiTomaso, S. Laha, and W. Rayess. Wireless Networks-on-Chips: Architecture, Wireless Channel, and Devices. IEEE Wireless Communications, 19(5), 2012."},{"key":"e_1_3_2_1_30_1","volume-title":"Lawrence Livermore National Laboratory","author":"McMahon F. H.","year":"1986","unstructured":"F. H. McMahon. The Livermore Fortran Kernels: A Computer Test Of The Numerical Performance Range. Technical report, Lawrence Livermore National Laboratory, 1986."},{"issue":"1","key":"e_1_3_2_1_31_1","first-page":"21","volume":"9","author":"Mellor-Crummey J. M.","year":"1991","unstructured":"J. M. Mellor-Crummey and M. L. Scott. Algorithms for Scalable Synchronization on Shared-memory Multiprocessors. ACM Transactions on Computer Systems, 9(1):21--65, 1991.","journal-title":"Algorithms for Scalable Synchronization on Shared-memory Multiprocessors. ACM Transactions on Computer Systems"},{"issue":"7","key":"e_1_3_2_1_32_1","first-page":"395","article-title":"Ethernet","volume":"19","author":"Metcalfe R. M.","year":"1976","unstructured":"R. M. Metcalfe and D. R. Boggs. Ethernet: Distributed Packet Switching for Local Computer Networks. Communications of the ACM, 19(7):395--404, 1976.","journal-title":"Distributed Packet Switching for Local Computer Networks. Communications of the ACM"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000078"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.5555\/2523721.2523764"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243783"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2011.2143650"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.23"},{"key":"e_1_3_2_1_38_1","volume-title":"International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)","author":"Scott S.","year":"1996","unstructured":"S. Scott. Synchronization and Communication in the T3E Multiprocessor. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 1996."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2049793"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.388040"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2007.4290322"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1038\/nature16454"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2347655.2347660"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2057950"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749723"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2297415"},{"key":"e_1_3_2_1_49_1","first-page":"25","volume-title":"Proceedings of the 9th European Microwave Integrated Circuits Conference","author":"Weissman N.","year":"2014","unstructured":"N. Weissman and E. Socher. 9mW 6Gbps Bi-directional 85-90GHz Transceiver in 65nm CMOS. In Proceedings of the 9th European Microwave Integrated Circuits Conference, pages 25--28, October 2014."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2014.2322995"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2386751"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250668"}],"event":{"name":"ASPLOS '16: Architectural Support for Programming Languages and Operating Systems","location":"Atlanta Georgia USA","acronym":"ASPLOS '16","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2872362.2872396","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2872362.2872396","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2872362.2872396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:41:31Z","timestamp":1763458891000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2872362.2872396"}},"subtitle":["An Architecture for Fast Synchronization through On-Chip Wireless Communication"],"short-title":[],"issued":{"date-parts":[[2016,3,25]]},"references-count":53,"alternative-id":["10.1145\/2872362.2872396","10.1145\/2872362"],"URL":"https:\/\/doi.org\/10.1145\/2872362.2872396","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2954679.2872396","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/2980024.2872396","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2016,3,25]]},"assertion":[{"value":"2016-03-25","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}