{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T10:15:24Z","timestamp":1775470524352,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":89,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T00:00:00Z","timestamp":1490400000000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-14-1-0148"],"award-info":[{"award-number":["FA9550-14-1-0148"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["N66001-14-1-4040, HR0011-13-2-0005"],"award-info":[{"award-number":["N66001-14-1-4040, HR0011-13-2-0005"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217553, CCF-1453112, CCF-1438980"],"award-info":[{"award-number":["CCF-1217553, CCF-1453112, CCF-1438980"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,3,25]]},"DOI":"10.1145\/2872362.2872414","type":"proceedings-article","created":{"date-parts":[[2016,3,28]],"date-time":"2016-03-28T09:24:30Z","timestamp":1459157070000},"page":"217-232","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":113,"title":["OpenPiton"],"prefix":"10.1145","author":[{"given":"Jonathan","family":"Balkind","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Michael","family":"McKeown","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Yaosheng","family":"Fu","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Tri","family":"Nguyen","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Yanqi","family":"Zhou","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Alexey","family":"Lavrov","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Mohammad","family":"Shahrad","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Adi","family":"Fuchs","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Samuel","family":"Payne","sequence":"additional","affiliation":[{"name":"Nvidia, Santa Clara, CA, USA"}]},{"given":"Xiaohua","family":"Liang","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Matthew","family":"Matl","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"David","family":"Wentzlaff","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]}],"member":"320","published-online":{"date-parts":[[2016,3,25]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"https:\/\/github.com\/CTSRD-CHERI\/beri. Accessed","author":"Beri","year":"2016","unstructured":"Beri processor 'arcina' release 1. https:\/\/github.com\/CTSRD-CHERI\/beri. Accessed Jan. 2016."},{"key":"e_1_3_2_1_2_1","volume-title":"https:\/\/github.com\/grantae\/mips32r1_xum. Accessed","author":"Xtensible Utah","year":"2016","unstructured":"eXtensible Utah Multicore (xum). https:\/\/github.com\/grantae\/mips32r1_xum. Accessed Jan. 2016."},{"key":"e_1_3_2_1_3_1","volume-title":"https:\/\/github.com\/grantae\/mips32r1_core. Accessed","year":"2016","unstructured":"Mips32 release 1. https:\/\/github.com\/grantae\/mips32r1_core. Accessed Jan. 2016."},{"key":"e_1_3_2_1_4_1","volume-title":"http:\/\/zet.aluzina.org\/index.php\/Zet_processor. Accessed","author":"Zet","year":"2016","unstructured":"Zet processor. http:\/\/zet.aluzina.org\/index.php\/Zet_processor. Accessed Jan. 2016."},{"key":"e_1_3_2_1_5_1","volume-title":"https:\/\/github.com\/zylin\/zpu. Accessed","author":"Zylin","year":"2016","unstructured":"Zylin cpu. https:\/\/github.com\/zylin\/zpu. Accessed Jan. 2016."},{"key":"e_1_3_2_1_6_1","unstructured":"OpenSPARC T1 Microarchitecture Specification. Santa Clara CA 2006."},{"key":"e_1_3_2_1_7_1","unstructured":"OpenSPARC T2 Core Microarchitecture Specification. Santa Clara CA 2007."},{"key":"e_1_3_2_1_8_1","volume-title":"Aemb multi-threaded 32-bit embedded core family. https:\/\/github.com\/aeste\/aemb. Accessed","author":"Works Aeste","year":"2016","unstructured":"\\relax Aeste Works. Aemb multi-threaded 32-bit embedded core family. https:\/\/github.com\/aeste\/aemb. Accessed Jan. 2016."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2764908"},{"key":"e_1_3_2_1_10_1","volume-title":"Open-source 32-bit risc soft-core processors. IOSR Journal od VLSI and Signal Processing, 2(4):43--46","author":"Balwaik R. R.","year":"2013","unstructured":"R. R. Balwaik, S. R. Nayak, and A. Jeyakumar. Open-source 32-bit risc soft-core processors. IOSR Journal od VLSI and Signal Processing, 2(4):43--46, 2013."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629579"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224318"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICISA.2014.6847416"},{"key":"e_1_3_2_1_16_1","first-page":"43","volume-title":"Proceedings of the 8th USENIX Conference on Operating Systems Design and Implementation, OSDI'08","author":"Boyd-Wickizer S.","year":"2008","unstructured":"S. Boyd-Wickizer, H. Chen, R. Chen, Y. Mao, F. Kaashoek, R. Morris, A. Pesterev, L. Stein, M. Wu, Y. Dai, Y. Zhang, and Z. Zhang. Corey: An operating system for many cores. In Proceedings of the 8th USENIX Conference on Operating Systems Design and Implementation, OSDI'08, pages 43--57, Berkeley, CA, USA, 2008. USENIX Association."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/1924943.1924944"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.66"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259028"},{"key":"e_1_3_2_1_20_1","unstructured":"D. J. Capelis. Lockbox: Helping computers keep your secrets. Technical Report UCSC-WASP-15-02 University of California Santa Cruz Nov. 2015."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"e_1_3_2_1_22_1","unstructured":"C. Celio D. A. Patterson and K. Asanovi\u0107. The berkeley out-of-order machine (boom): An industry-competitive synthesizable parameterized risc-v processor. Technical Report UCB\/EECS-2015--167 EECS Department University of California Berkeley Jun 2015."},{"key":"e_1_3_2_1_23_1","first-page":"1","volume-title":"IEEE 16th Int. Symposium on","author":"Champagne D.","year":"2010","unstructured":"D. Champagne and R. Lee. Scalable architectural support for trusted software. In High Performance Computer Architecture (HPCA), IEEE 16th Int. Symposium on, pages 1--12, Jan 2010."},{"key":"e_1_3_2_1_24_1","volume-title":"Grlib ip core user's manual","author":"Cobham Gaisler","year":"2015","unstructured":"\\relax Cobham Gaisler AB. Grlib ip core user's manual. May 2015."},{"key":"e_1_3_2_1_25_1","first-page":"813","volume-title":"Methods and Tools (DSD), 2010 13th Euromicro Conference on","author":"da Silva A.","year":"2010","unstructured":"A. da Silva and S. Sanchez. Leon3 vip: A virtual platform with fault injection capabilities. In Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th Euromicro Conference on, pages 813--816, Sept 2010."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509664"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2013.75"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694353"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830832"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844467"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/233551.233553"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2011.6008574"},{"key":"e_1_3_2_1_34_1","unstructured":"HT-Lab. Cpu86: 8088 fpga ip core. http:\/\/ht-lab.com\/freecores\/cpu8086\/cpu86.html. Accessed Jan. 2016."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147161"},{"key":"e_1_3_2_1_36_1","volume-title":"Msp430x1xx family user's guide","author":"Instruments T.","year":"2006","unstructured":"T. Instruments. Msp430x1xx family user's guide, 2006."},{"key":"e_1_3_2_1_37_1","first-page":"1","volume-title":"Field Programmable Logic and Applications (FPL), 2014 24th International Conference on","author":"Jia R.","year":"2014","unstructured":"R. Jia, C. Lin, Z. Guo, R. Chen, F. Wang, T. Gao, and H. Yang. A survey of open source processors for fpgas. In Field Programmable Logic and Applications (FPL), 2014 24th International Conference on, pages 1--6, Sept 2014."},{"key":"e_1_3_2_1_38_1","first-page":"75","volume-title":"IEEE Int. Symposium on","author":"Khalid O.","year":"2013","unstructured":"O. Khalid, C. Rolfes, and A. Ibing. On implementing trusted boot for embedded systems. In Hardware-Oriented Security and Trust, IEEE Int. Symposium on, pages 75--80, June 2013."},{"key":"e_1_3_2_1_39_1","first-page":"1","article-title":"Designing and implementing malicious hardware","volume":"8","author":"King S. T.","year":"2008","unstructured":"S. T. King, J. Tucek, A. Cozzie, C. Grier, W. Jiang, and Y. Zhou. Designing and implementing malicious hardware. LEET, 8:1--8, 2008.","journal-title":"LEET"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837369"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942056"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2011.5937096"},{"key":"e_1_3_2_1_45_1","volume-title":"Embedded software development with eCos","author":"Massa A. J.","year":"2003","unstructured":"A. J. Massa. Embedded software development with eCos. Prentice Hall Professional, 2003."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.43"},{"key":"e_1_3_2_1_47_1","volume-title":"The extensible utah multicore project. Master's thesis","author":"Meakin B. L.","year":"2010","unstructured":"B. L. Meakin. Multicore system design with xum: The extensible utah multicore project. Master's thesis, The University of Utah, 2010."},{"key":"e_1_3_2_1_48_1","first-page":"648","volume-title":"Third International Conference on","author":"Mehdizadeh N.","year":"2008","unstructured":"N. Mehdizadeh, M. Shokrolah-Shirazi, and S. Miremadi. Analyzing fault effects in the 32-bit openrisc 1200 microprocessor. In Availability, Reliability and Security. ARES 08. Third International Conference on, pages 648--652, March 2008."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176877"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"e_1_3_2_1_51_1","volume-title":"November","author":"Ngiap S. T. S.","year":"2007","unstructured":"S. T. S. Ngiap. Aemb 32-bit microprocessor core datasheet, November 2007."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/EDUCON.2010.5492390"},{"key":"e_1_3_2_1_53_1","unstructured":"OpenCores. Altor32 - alternative lightweight openrisc cpu. http:\/\/opencores.org\/project altor32. Accessed Jan. 2016."},{"key":"e_1_3_2_1_54_1","unstructured":"OpenCores. Amber arm-compatible core. http:\/\/opencores.org\/project amber. Accessed Jan. 2016."},{"key":"e_1_3_2_1_55_1","volume-title":"http:\/\/opencores.org\/project,openmsp430. Accessed","year":"2016","unstructured":"OpenCores. Openmsp430. http:\/\/opencores.org\/project,openmsp430. Accessed Jan. 2016."},{"key":"e_1_3_2_1_56_1","unstructured":"OpenCores. Or1200 openrisc processor. http:\/\/opencores.org\/or1k\/OR1200_OpenRISC_Processor. Accessed Jan. 2016."},{"key":"e_1_3_2_1_57_1","unstructured":"OpenCores. pAVR. http:\/\/opencores.org\/project pavr. Accessed Jan. 2016."},{"key":"e_1_3_2_1_58_1","unstructured":"Oracle. OpenSPARC T1. http:\/\/www.oracle.com\/technetwork\/systems\/opensparc\/opensparc-t1-page-1%444609.html."},{"key":"e_1_3_2_1_59_1","first-page":"1","volume-title":"17th Euro micro conf. on real time systems","author":"Ortego P. M.","year":"2004","unstructured":"P. M. Ortego and P. Sack. Sesc: Superescalar simulator. In 17th Euro micro conf. on real time systems, pages 1--4, 2004."},{"key":"e_1_3_2_1_60_1","volume-title":"Fourth Workshop on Silicon Errors in Logic-System Effects (SELSE). Citeseer","author":"Parulkar I.","year":"2008","unstructured":"I. Parulkar, A. Wood, J. C. Hoe, B. Falsafi, S. V. Adve, J. Torrellas, and S. Mitra. Opensparc: An open platform for hardware reliability experimentation. In Fourth Workshop on Silicon Errors in Logic-System Effects (SELSE). Citeseer, 2008."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176660"},{"key":"e_1_3_2_1_62_1","volume-title":"Springer Science & Business Media","author":"Polychronopoulos C. D.","year":"2012","unstructured":"C. D. Polychronopoulos. Parallel programming and compilers, volume 59. Springer Science & Business Media, 2012."},{"key":"e_1_3_2_1_63_1","unstructured":"PyHP. PyHP Official Home Page. http:\/\/pyhp.sourceforge.net."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254082"},{"key":"e_1_3_2_1_65_1","volume-title":"March","author":"Aeroflex Gaisler","year":"2010","unstructured":"\\relax Aeroflex Gaisler AB. Sparc v8 32-bit processor leon3\/leon3-ft companioncore data sheet, March 2010."},{"key":"e_1_3_2_1_66_1","volume-title":"The berkeley out-of-order risc-v processor. https:\/\/github.com\/ucb-bar\/riscv-boom. Accessed","author":"Berkeley Architecture Research UC","year":"2016","unstructured":"\\relax UC Berkeley Architecture Research. The berkeley out-of-order risc-v processor. https:\/\/github.com\/ucb-bar\/riscv-boom. Accessed Jan. 2016."},{"key":"e_1_3_2_1_67_1","volume-title":"Rocket core. https:\/\/github.com\/ucb-bar\/rocket. Accessed","author":"Berkeley Architecture Research UC","year":"2016","unstructured":"\\relax UC Berkeley Architecture Research. Rocket core. https:\/\/github.com\/ucb-bar\/rocket. Accessed Jan. 2016."},{"key":"e_1_3_2_1_68_1","unstructured":"S. RISC. Simply risc s1 core. http:\/\/www.srisc.com\/?s1. Accessed Jan. 2016."},{"key":"e_1_3_2_1_69_1","volume-title":"Xilinx\u00ae Xcell J","author":"Schaumont P.","year":"2003","unstructured":"P. Schaumont and I. Verbauwhede. Thumbpod puts security under your thumb. Xilinx\u00ae Xcell J, 2003."},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/1360612.1360617"},{"key":"e_1_3_2_1_71_1","unstructured":"L. Semiconductor. Latticemico32 open free 32-bit soft processor. http:\/\/www.latticesemi.com\/en\/Products\/DesignSoftwareAndIP\/Intellectual%Property\/IPCore\/IPCores02\/LatticeMico32.aspx. Accessed Jan. 2016."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665689"},{"key":"e_1_3_2_1_73_1","first-page":"016","article-title":"Soc verification platform based on aemb softcore processor [j]","volume":"4","author":"Shengfeng S.","year":"2010","unstructured":"S. Shengfeng, Z. Dexue, and Y. Guoping. Soc verification platform based on aemb softcore processor [j]. Microcontrollers & Embedded Systems, 4:016, 2010.","journal-title":"Microcontrollers & Embedded Systems"},{"key":"e_1_3_2_1_74_1","volume-title":"Proc. of Workshop on SELSE","author":"Smolens J. C.","year":"2007","unstructured":"J. C. Smolens, B. T. Gold, J. C. Hoe, B. Falsafi, and K. Mai. Detecting emerging wearout faults. In Proc. of Workshop on SELSE, 2007."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516660"},{"key":"e_1_3_2_1_76_1","volume-title":"ASEE Southeast Section Conference","author":"Strelzoff A.","year":"2007","unstructured":"A. Strelzoff. Teaching computer architecture with fpga soft processors. In ASEE Southeast Section Conference, 2007."},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151022"},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2011.5929973"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.5555\/2123870.2123876"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2006.373294"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"issue":"1","key":"e_1_3_2_1_82_1","first-page":"29","article-title":"An 80-tile sub-100-w teraflops processor in 65-nm cmos. Solid-State Circuits","volume":"43","author":"Vangal S. R.","year":"2008","unstructured":"S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, et al. An 80-tile sub-100-w teraflops processor in 65-nm cmos. Solid-State Circuits, IEEE Journal of, 43(1):29--41, 2008.","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_83_1","unstructured":"R. N. M. Watson J. Woodruff D. Chisnall B. Davis W. Koszek A. T. Markettos S. W. Moore S. J. Murdoch P. G. Neumann R. Norton and M. Roe. Bluespec Extensible RISC Implementation: BERI Hardware reference. Technical Report UCAM-CL-TR-868 University of Cambridge Computer Laboratory Apr. 2015."},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378780"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807132"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237040"},{"key":"e_1_3_2_1_87_1","volume-title":"Extending amdahl's law for energy-efficient computing in the many-core era. Computer, (12):24--31","author":"Woo D. H.","year":"2008","unstructured":"D. H. Woo and H.-H. S. Lee. Extending amdahl's law for energy-efficient computing in the many-core era. Computer, (12):24--31, 2008."},{"issue":"3","key":"e_1_3_2_1_88_1","first-page":"272","article-title":"Design Test of Computers","volume":"25","author":"Yeh D.","year":"2008","unstructured":"D. Yeh, L.-S. Peh, S. Borkar, J. Darringer, A. Agarwal, and W.-M. Hwu. Thousand-core chips [roundtable]. Design Test of Computers, IEEE, 25(3):272--278, May 2008.","journal-title":"IEEE"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2010.5548320"}],"event":{"name":"ASPLOS '16: Architectural Support for Programming Languages and Operating Systems","location":"Atlanta Georgia USA","acronym":"ASPLOS '16","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2872362.2872414","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2872362.2872414","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2872362.2872414","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:40:14Z","timestamp":1763458814000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2872362.2872414"}},"subtitle":["An Open Source Manycore Research Framework"],"short-title":[],"issued":{"date-parts":[[2016,3,25]]},"references-count":89,"alternative-id":["10.1145\/2872362.2872414","10.1145\/2872362"],"URL":"https:\/\/doi.org\/10.1145\/2872362.2872414","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2954679.2872414","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/2980024.2872414","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2016,3,25]]},"assertion":[{"value":"2016-03-25","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}