{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:34Z","timestamp":1750306294510,"version":"3.41.0"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,5,12]],"date-time":"2016-05-12T00:00:00Z","timestamp":1463011200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"ERC","award":["DESHYMAG (334845)"],"award-info":[{"award-number":["DESHYMAG (334845)"]}]},{"name":"European Union under the European Research Council","award":["HYMAGINE (246942)"],"award-info":[{"award-number":["HYMAGINE (246942)"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2016,7,26]]},"abstract":"<jats:p>The most widely used embedded memory technology, static random access memory (SRAM), is heading toward scaling problems in advanced technology nodes due to the leakage currents caused by the quantum tunneling effect. As an alternative, spin-transfer torque magnetic RAM (STT-MRAM) technology shows comparable performance in terms of speed and power consumption and much better performance in terms of density and leakage. Moreover, MRAM brings up new paradigms in system design thanks to its inherent nonvolatility, which allows the definition of new instant-on\/off policies and leakage current optimization. Based on our compact model, we have developed a fully characterized system-on-chip from the basic cell up to the system architecture in a 40nm LP hybrid CMOS\/magnetic process. Through simulations, first we demonstrate that STT-MRAM is a candidate for the memory part of embedded systems, and second we implement a check-pointing methodology based on the regular interrupt routines of a processor to enable a fast power on and off functionality. Using a synthetic benchmark developed in high-level programming languages intended to be representative of integer system performance, our method shows that having MRAM instead of SRAM in an embedded design brings up important energy savings. The influence of the check-pointing routine on power consumption is finally evaluated with regard to various shutdown and restart behaviors.<\/jats:p>","DOI":"10.1145\/2876507","type":"journal-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T14:30:58Z","timestamp":1463149858000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories"],"prefix":"10.1145","volume":"12","author":[{"given":"Christophe","family":"Layer","sequence":"first","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Laurent","family":"Becker","sequence":"additional","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Kotb","family":"Jabeur","sequence":"additional","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Sylvain","family":"Claireux","sequence":"additional","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Bernard","family":"Dieny","sequence":"additional","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Guillaume","family":"Prenat","sequence":"additional","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Gregory Di","family":"Pendina","sequence":"additional","affiliation":[{"name":"Spintec, Grenoble, France"}]},{"given":"Stephane","family":"Gros","sequence":"additional","affiliation":[{"name":"eVaderis, Grenoble, France"}]},{"given":"Pierre","family":"Paoli","sequence":"additional","affiliation":[{"name":"eVaderis, Grenoble, France"}]},{"given":"Virgile","family":"Javerliac","sequence":"additional","affiliation":[{"name":"eVaderis, Grenoble, France"}]},{"given":"Fabrice","family":"Bernard-Granger","sequence":"additional","affiliation":[{"name":"eVaderis, Grenoble, France"}]},{"given":"Loic","family":"Decloedt","sequence":"additional","affiliation":[{"name":"eVaderis, Grenoble, France"}]}],"member":"320","published-online":{"date-parts":[[2016,5,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.54.9353"},{"volume-title":"Proceedings of the MOS-AK Workshop of the Design and Test in Europe Conference (DATE\u201915)","year":"2015","author":"Bernard-Granger Fabrice","key":"e_1_2_1_2_1"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977293"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.198"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522314"},{"volume-title":"Federal Information Processing Standards, Publication 197","author":"Daemen Joan","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3680013"},{"key":"e_1_2_1_8_1","first-page":"16","article-title":"Spin-transfer torque switching in magnetic tunnel junctions and spin-transfer torque random access memory","volume":"19","author":"Diao Zhitao","year":"2007","journal-title":"Journal of Physics"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2015.7150308"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/NVMTS.2014.7060834"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2770287.2770295"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1952.273898"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2976435"},{"volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201914)","author":"Ikegami K.","key":"e_1_2_1_14_1"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.1083"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.3844\/ajassp.2014.119.126"},{"key":"e_1_2_1_17_1","first-page":"7","article-title":"Basic principles of STT-MRAM cell operation in memory arrays","volume":"46","author":"Khvalkovskiy A. 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