{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:39:43Z","timestamp":1773247183412,"version":"3.50.1"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,5,27]],"date-time":"2016-05-27T00:00:00Z","timestamp":1464307200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Swiss Government Excellence Scholarship"},{"name":"HiPer Consortium under the \u201cMagnet\u201d program of the office of the chief scientist in the Israeli Ministry of Economy"},{"name":"FP7 project PHIDIAS","award":["g.a. 318013"],"award-info":[{"award-number":["g.a. 318013"]}]},{"name":"Nano-Tera.ch with Swiss Confederation financing under the IcySoC project"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2016,9,22]]},"abstract":"<jats:p>Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors through memory generators, targeted at rather generic design specifications. As an alternative, standard cell memories (SCMs) can be defined, synthesized, and placed and routed as an integral part of a given digital system, providing complete design flexibility, good energy efficiency, low-voltage operation, and even area efficiency for small memory blocks. Yet implementing an SCM block with a standard digital flow often fails to exploit the distinct and regular structure of such an array, leaving room for optimization. In this article, we present a design methodology for optimizing the physical implementation of SCM macros as part of the standard design flow. This methodology introduces controlled placement, leading to a structured, noncongested layout with close to 100% placement utilization, resulting in a smaller silicon footprint, reduced wire length, and lower power consumption compared to SCMs without controlled placement. This methodology is demonstrated on SCM macros of various sizes and aspect ratios in a state-of-the-art 28nm fully depleted silicon-on-insulator technology, and compared with equivalent macros designed with the noncontrolled, standard flow, as well as with foundry-supplied SRAM macros. The controlled SCMs provide an average 25% reduction in area as compared to noncontrolled implementations while achieving a smaller size than SRAM macros of up to 1Kbyte. Power and performance comparisons of controlled SCM blocks of a commonly found 256 \u00d7 32 (1 Kbyte) memory with foundry-provided SRAMs show greater than 65% and 10% reduction in read and write power, respectively, while providing faster access than their SRAM counterparts, despite being of an aspect ratio that is typically unfavorable for SCMs. In addition, the SCM blocks function correctly with a supply voltage as low as 0.3V, well below the lower limit of even the SRAM macros optimized for low-voltage operation. The controlled placement methodology is applied within a full-chip physical implementation flow of an OpenRISC-based test chip, providing more than 50% power reduction compared to equivalently sized compiled SRAMs under a benchmark application.<\/jats:p>","DOI":"10.1145\/2890498","type":"journal-article","created":{"date-parts":[[2016,5,31]],"date-time":"2016-05-31T12:15:09Z","timestamp":1464696909000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":49,"title":["Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement"],"prefix":"10.1145","volume":"21","author":[{"given":"Adam","family":"Teman","sequence":"first","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Bar-Ilan University, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Rossi","sequence":"additional","affiliation":[{"name":"University of Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pascal","family":"Meinerzhagen","sequence":"additional","affiliation":[{"name":"Bar-Ilan University, Ramat Gan, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"University of Bologna, ETH-Zurich, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Burg","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,5,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649106"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/605459.605461"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2631640"},{"key":"e_1_2_1_5_1","unstructured":"ITRS. 2015. International Technology Roadmap for Semiconductors 2015 Edition. Available at http:\/\/www.itrs2.net\/itrs-reports.html.  ITRS. 2015. International Technology Roadmap for Semiconductors 2015 Edition. Available at http:\/\/www.itrs2.net\/itrs-reports.html."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373428"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548579"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2162159"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341319"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168911"},{"key":"e_1_2_1_11_1","volume-title":"The OpenRISC Project. Retrieved","year":"2016","unstructured":"OpenCores.org. 2015. The OpenRISC Project. Retrieved April 7, 2016 , from http:\/\/opencores.org\/or1k. OpenCores.org. 2015. The OpenRISC Project. Retrieved April 7, 2016, from http:\/\/opencores.org\/or1k."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242497"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2295027"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032493"},{"key":"e_1_2_1_15_1","volume-title":"Harris","author":"Sutherland Ivan Edward","year":"1999","unstructured":"Ivan Edward Sutherland , Robert F. Sproull , and David F . Harris . 1999 . Logical Effort : Designing Fast CMOS Circuits. Morgan Kaufmann . Ivan Edward Sutherland, Robert F. Sproull, and David F. Harris. 1999. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164009"},{"key":"e_1_2_1_17_1","volume-title":"Proceedings of the 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915)","author":"Teman A.","year":"2015","unstructured":"A. Teman , D. Rossi , P. Meinerzhagen , L. Benini , and A. Burg . 2015. Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI . In Proceedings of the 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915) . 81--86. DOI:http:\/\/dx.doi.org\/10.1109\/ ASPDAC. 2015 .7058985 A. Teman, D. Rossi, P. Meinerzhagen, L. Benini, and A. Burg. 2015. Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. In Proceedings of the 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915). 81--86. DOI:http:\/\/dx.doi.org\/10.1109\/ ASPDAC.2015.7058985"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2358699"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907996"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001903"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2890498","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2890498","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:38:55Z","timestamp":1750221535000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2890498"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,27]]},"references-count":21,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2016,9,22]]}},"alternative-id":["10.1145\/2890498"],"URL":"https:\/\/doi.org\/10.1145\/2890498","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,5,27]]},"assertion":[{"value":"2015-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-05-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}