{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T18:37:12Z","timestamp":1775155032381,"version":"3.50.1"},"reference-count":25,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,5,12]],"date-time":"2016-05-12T00:00:00Z","timestamp":1463011200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2016,7,26]]},"abstract":"<jats:p>Due to their nonvolatile nature, excellent scalability, and high density, memristive nanodevices provide a promising solution for low-cost on-chip storage. Integrating memristor-based synaptic crossbars into digital neuromorphic processors (DNPs) may facilitate efficient realization of brain-inspired computing. This article investigates architectural design exploration of DNPs with memristive synapses by proposing two synapse readout schemes. The key design tradeoffs involving different analog-to-digital conversions and memory accessing styles are thoroughly investigated. A novel storage strategy optimized for feedforward neural networks is proposed in this work, which greatly reduces the energy and area cost of the memristor array and its peripherals.<\/jats:p>","DOI":"10.1145\/2894756","type":"journal-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T14:30:58Z","timestamp":1463149858000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":25,"title":["Neuromorphic Processors with Memristive Synapses"],"prefix":"10.1145","volume":"12","author":[{"given":"Qian","family":"Wang","sequence":"first","affiliation":[{"name":"Texas A&amp;M University, College Station, TX"}]},{"given":"Yongtae","family":"Kim","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara, CA"}]},{"given":"Peng","family":"Li","sequence":"additional","affiliation":[{"name":"Texas A&amp;M University, College Station, TX"}]}],"member":"320","published-online":{"date-parts":[[2016,5,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2012.6252637"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00521-013-1501-0"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687491"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228448"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2092170"},{"key":"e_1_2_1_7_1","volume-title":"Null","author":"Huang Zhaohui","unstructured":"Zhaohui Huang and Peixin Zhong . 2004. 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