{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:47:28Z","timestamp":1756000048161,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,9,2]],"date-time":"2016-09-02T00:00:00Z","timestamp":1472774400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Project PowerEval","award":["IUK314\/001"],"award-info":[{"award-number":["IUK314\/001"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2016,9,22]]},"abstract":"<jats:p>In this article, we investigate a hierarchical statistical leakage analysis (HSLA) design flow where module-level statistical leakage models supplied by IP vendors are used to improve the efficiency and capacity of SoC statistical leakage power analysis. To solve the challenges of incorporating spatial correlations between IP modules at system level, we first propose a method to extract correlation-inclusive leakage models. Then a method to handle the spatial correlations at system level is proposed. Using this method, the runtime of system statistical leakage analysis (SLA) can be significantly improved without disclosing the netlists of the IP modules. Experimental results demonstrate that the proposed HSLA method is about 100 times faster than gate-level full-chip SLA methods while maintaining the accuracy. In addition, we also investigate one application of this HSLA method, a leakage-yield-driven floorplanning framework, to demonstrate the benefits of such an HSLA method in practice. Moreover, an optimized hierarchical leakage analysis method dedicated to the floorplanning framework is proposed. The effectiveness of the floorplanning framework and the optimized method are confirmed by extensive experimental results.<\/jats:p>","DOI":"10.1145\/2896820","type":"journal-article","created":{"date-parts":[[2016,9,2]],"date-time":"2016-09-02T14:33:50Z","timestamp":1472826830000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Hierarchical Statistical Leakage Analysis and Its Application"],"prefix":"10.1145","volume":"21","author":[{"given":"Yang","family":"Xu","sequence":"first","affiliation":[{"name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J\u00fcrgen","family":"Teich","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg (FAU), Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,9,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065716"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2008.2011629"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1176254.1176284"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.150"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357998"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996800"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.122"},{"volume-title":"Principal Component Analysis","author":"Jolliffe I. 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A case for thermal-aware floorplanning at the microarchitectural level . Journal of Instruction-Level Parallelism 7 , 1 -- 16 . K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron. 2005. A case for thermal-aware floorplanning at the microarchitectural level. Journal of Instruction-Level Parallelism 7, 1--16.","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"e_1_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Ruijing Shen Ning Mi Sheldon X.-D. Tan Yici Cai and Xianlong Hong. 2009. Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. In ASP-DAC. 161--166.   Ruijing Shen Ning Mi Sheldon X.-D. Tan Yici Cai and Xianlong Hong. 2009. Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. 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