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Unfortunately, converting an algorithm by hand to a hardware description language suitable for compilation on these platforms is frequently too time consuming to be practical. Recent work on hardware synthesis of high-level image processing languages demonstrated that a single-rate pipeline of stencil kernels can be synthesized into hardware with provably minimal buffering. Unfortunately, few advanced image processing or vision algorithms fit into this highly-restricted programming model.<\/jats:p>\n          <jats:p>In this paper, we present Rigel, which takes pipelines specified in our new multi-rate architecture and lowers them to FPGA implementations. Our flexible multi-rate architecture supports pyramid image processing, sparse computations, and space-time implementation tradeoffs. We demonstrate depth from stereo, Lucas-Kanade, the SIFT descriptor, and a Gaussian pyramid running on two FPGA boards. Our system can synthesize hardware for FPGAs with up to 436 Megapixels\/second throughput, and up to 297x faster runtime than a tablet-class ARM CPU.<\/jats:p>","DOI":"10.1145\/2897824.2925892","type":"journal-article","created":{"date-parts":[[2016,7,11]],"date-time":"2016-07-11T16:04:33Z","timestamp":1468253073000},"page":"1-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":56,"title":["Rigel"],"prefix":"10.1145","volume":"35","author":[{"given":"James","family":"Hegarty","sequence":"first","affiliation":[{"name":"Stanford University"}]},{"given":"Ross","family":"Daly","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Zachary","family":"DeVito","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Jonathan","family":"Ragan-Kelley","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[{"name":"Stanford University"}]},{"given":"Pat","family":"Hanrahan","sequence":"additional","affiliation":[{"name":"Stanford University"}]}],"member":"320","published-online":{"date-parts":[[2016,7,11]]},"reference":[{"key":"e_1_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1778765.1778766"},{"key":"e_1_2_2_2_1","unstructured":"Adelson E. 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