{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T17:10:53Z","timestamp":1781370653815,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,5,18]],"date-time":"2016-05-18T00:00:00Z","timestamp":1463529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"the Beijing Municipal Science and Technology Commission of China","award":["D151100000815003"],"award-info":[{"award-number":["D151100000815003"]}]},{"name":"the National High Technology Research and Development Program of China","award":["2013AA013201"],"award-info":[{"award-number":["2013AA013201"]}]},{"name":"the National Natural Science Foundation of China","award":["61232003, 61433008"],"award-info":[{"award-number":["61232003, 61433008"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,5,18]]},"DOI":"10.1145\/2902961.2902967","type":"proceedings-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T18:21:10Z","timestamp":1463163670000},"page":"397-402","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["Exploring Main Memory Design Based on Racetrack Memory Technology"],"prefix":"10.1145","author":[{"given":"Qingda","family":"Hu","sequence":"first","affiliation":[{"name":"Department of Computer Science and Technology, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Guangyu","family":"Sun","sequence":"additional","affiliation":[{"name":"CECA, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiwu","family":"Shu","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Technology, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chao","family":"Zhang","sequence":"additional","affiliation":[{"name":"CECA, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2016,5,18]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593161"},{"key":"e_1_3_2_1_6_1","volume-title":"Morgan Kaufmann","author":"Jacob B.","year":"2010","unstructured":"B. Jacob Memory systems: cache, DRAM, disk . Morgan Kaufmann , 2010 . B. Jacob et al. Memory systems: cache, DRAM, disk. Morgan Kaufmann, 2010."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168944"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/2014698.2014871"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370869"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593137"},{"key":"e_1_3_2_1_13_1","volume-title":"Stream benchmark. www.cs.virginia.edu\/stream\/ref.html","author":"McCalpin J.","year":"1995","unstructured":"J. McCalpin . Stream benchmark. www.cs.virginia.edu\/stream\/ref.html , 1995 . J. McCalpin. Stream benchmark. www.cs.virginia.edu\/stream\/ref.html, 1995."},{"key":"e_1_3_2_1_14_1","volume-title":"8Gb: x4, x8, x16 DDR3L SDRAM Description. www.micron.com","year":"2015","unstructured":"Micron. 8Gb: x4, x8, x16 DDR3L SDRAM Description. www.micron.com , 2015 . Micron. 8Gb: x4, x8, x16 DDR3L SDRAM Description. www.micron.com, 2015."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_3_2_1_17_1","volume-title":"DATE","author":"Ranjan A.","year":"2015","unstructured":"A. Ranjan : a dynamically reconfigurable cache using domain wall memory tapes . In DATE , 2015 . A. Ranjan et al. Dyrectape: a dynamically reconfigurable cache using domain wall memory tapes. In DATE, 2015."},{"key":"e_1_3_2_1_18_1","volume-title":"DATE","author":"Sun G.","year":"2015","unstructured":"G. Sun From device to system: cross-layer design exploration of racetrack memory . In DATE , 2015 . G. Sun et al. From device to system: cross-layer design exploration of racetrack memory. In DATE, 2015."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627651"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488799"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.16"},{"key":"e_1_3_2_1_22_1","volume-title":"ISCA","author":"Venkatesan R.","year":"2014","unstructured":"R. Venkatesan : Spintronic-tape architecture for gpgpu cache hierarchies . In ISCA , 2014 . R. Venkatesan et al. Stag: Spintronic-tape architecture for gpgpu cache hierarchies. In ISCA, 2014."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/225830.223990"},{"key":"e_1_3_2_1_24_1","volume-title":"ASP-DAC","author":"Zhang C.","year":"2015","unstructured":"C. Zhang Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power . In ASP-DAC , 2015 . C. Zhang et al. Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. In ASP-DAC, 2015."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"}],"event":{"name":"GLSVLSI '16: Great Lakes Symposium on VLSI 2016","location":"Boston Massachusetts USA","acronym":"GLSVLSI '16","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"]},"container-title":["Proceedings of the 26th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2902967","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2902961.2902967","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:39:03Z","timestamp":1750221543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2902967"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,18]]},"references-count":25,"alternative-id":["10.1145\/2902961.2902967","10.1145\/2902961"],"URL":"https:\/\/doi.org\/10.1145\/2902961.2902967","relation":{},"subject":[],"published":{"date-parts":[[2016,5,18]]},"assertion":[{"value":"2016-05-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}