{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:29Z","timestamp":1750306289307,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,5,18]],"date-time":"2016-05-18T00:00:00Z","timestamp":1463529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,5,18]]},"DOI":"10.1145\/2902961.2902991","type":"proceedings-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T18:21:10Z","timestamp":1463163670000},"page":"365-368","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths"],"prefix":"10.1145","author":[{"given":"Tuhin Subhra","family":"Chakraborty","sequence":"first","affiliation":[{"name":"Broadcom Limited, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Santanu","family":"Kundu","sequence":"additional","affiliation":[{"name":"Broadcom Limited, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deepak","family":"Agrawal","sequence":"additional","affiliation":[{"name":"Broadcom Limited, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay Tanaji","family":"Shinde","sequence":"additional","affiliation":[{"name":"Broadcom Limited, Allentown, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob","family":"Mathews","sequence":"additional","affiliation":[{"name":"Broadcom Limited, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rekha K.","family":"James","sequence":"additional","affiliation":[{"name":"Cochin University of Science & Technology, Kochi, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,5,18]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Leakage in nanometer CMOS technologies,\" Springer","author":"Narendra S.","year":"2006","unstructured":"S. Narendra and A. Chandrakasan , \" Leakage in nanometer CMOS technologies,\" Springer , 2006 . S. Narendra and A. Chandrakasan, \"Leakage in nanometer CMOS technologies,\" Springer, 2006."},{"key":"e_1_3_2_1_2_1","first-page":"496","article-title":"Cell library management for power optimization","volume":"7","author":"Turner M. F.","year":"2009","unstructured":"M. F. Turner , J. W. Byrn , and J. S. Brown , \" Cell library management for power optimization ,\" Us patent -- US 7 , 496 ,867 B2, 2009 . M. F. Turner, J. W. Byrn, and J. S. Brown, \"Cell library management for power optimization,\" Us patent -- US 7,496,867 B2, 2009.","journal-title":"Us patent -- US"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.748196"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309975"},{"key":"e_1_3_2_1_5_1","first-page":"205","article-title":"Low power design using dual threshold voltage","author":"Ho Y.","year":"2004","unstructured":"Y. Ho and T. Hwang , \" Low power design using dual threshold voltage ,\" Proc. of the Conference on Asia South Pacific Design Automation , pp. 205 -- 208 , 2004 . Y. Ho and T. Hwang, \"Low power design using dual threshold voltage,\" Proc. of the Conference on Asia South Pacific Design Automation, pp. 205--208, 2004.","journal-title":"Proc. of the Conference on Asia South Pacific Design Automation"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.924061"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024829"},{"key":"e_1_3_2_1_8_1","first-page":"B2","article-title":"Granular channel width for power optimization","volume":"8196086","author":"Brown J. S.","year":"2012","unstructured":"J. S. Brown , J. W. Byrn , and M. F. Turner , \" Granular channel width for power optimization ,\" US patent -- US 8196086 B2 , 2012 . J. S. Brown, J. W. Byrn, and M. F. Turner, \"Granular channel width for power optimization,\" US patent -- US 8196086 B2, 2012.","journal-title":"US patent -- US"}],"event":{"name":"GLSVLSI '16: Great Lakes Symposium on VLSI 2016","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Boston Massachusetts USA","acronym":"GLSVLSI '16"},"container-title":["Proceedings of the 26th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2902991","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2902961.2902991","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:39:03Z","timestamp":1750221543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2902991"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,18]]},"references-count":8,"alternative-id":["10.1145\/2902961.2902991","10.1145\/2902961"],"URL":"https:\/\/doi.org\/10.1145\/2902961.2902991","relation":{},"subject":[],"published":{"date-parts":[[2016,5,18]]},"assertion":[{"value":"2016-05-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}