{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:29Z","timestamp":1750306289259,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":10,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,5,18]],"date-time":"2016-05-18T00:00:00Z","timestamp":1463529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,5,18]]},"DOI":"10.1145\/2902961.2903005","type":"proceedings-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T18:21:10Z","timestamp":1463163670000},"page":"117-120","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques"],"prefix":"10.1145","author":[{"given":"Nidhi","family":"Batra","sequence":"first","affiliation":[{"name":"IIIT-Delhi, New Delhi, India"}]},{"given":"Pawan","family":"Sehgal","sequence":"additional","affiliation":[{"name":"IIIT-Delhi, New Delhi, India"}]},{"given":"Shashwat","family":"Kaushik","sequence":"additional","affiliation":[{"name":"IIIT-Delhi, New Delhi, India"}]},{"given":"Mohammad S.","family":"Hashmi","sequence":"additional","affiliation":[{"name":"IIIT-Delhi, New Delhi, India"}]},{"given":"Sudesh","family":"Bhalla","sequence":"additional","affiliation":[{"name":"ST Microelectronics, Greater Noida, India"}]},{"given":"Anuj","family":"Grover","sequence":"additional","affiliation":[{"name":"ST Microelectronics, Greater Noida, India"}]}],"member":"320","published-online":{"date-parts":[[2016,5,18]]},"reference":[{"volume-title":"International technology roadmap for semiconductors","year":"2004","key":"e_1_3_2_1_1_1","unstructured":"International Technology Roadmap for Semiconductors , International technology roadmap for semiconductors 2004 . International Technology Roadmap for Semiconductors, International technology roadmap for semiconductors 2004."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.134"},{"key":"e_1_3_2_1_3_1","first-page":"15","volume-title":"Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits,\" Symposium on VLSl Technology Digest of Technical Papers","author":"Burnett D.","year":"1994","unstructured":"D. Burnett , K. Erington , C. Subramanian and K. Baker , \" Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits,\" Symposium on VLSl Technology Digest of Technical Papers , pp. 15 -- 16 , 1994 . D. Burnett, K. Erington, C. Subramanian and K. Baker, \"Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits,\" Symposium on VLSl Technology Digest of Technical Papers, pp. 15--16, 1994."},{"key":"e_1_3_2_1_4_1","author":"Bhavnagarwala A. J.","year":"2001","unstructured":"A. J. Bhavnagarwala , X. Tang and J. D. Meindl , \"The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability,\" in IEEE Journal of Solid-State Circuits , April 2001 . A. J. Bhavnagarwala, X. Tang and J. D. Meindl, \"The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability,\" in IEEE Journal of Solid-State Circuits, April 2001.","journal-title":"\"The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability,\" in IEEE Journal of Solid-State Circuits"},{"issue":"4","key":"e_1_3_2_1_5_1","first-page":"6","volume":"31","author":"Gong F.","year":"2014","unstructured":"F. Gong , H. Yu , Y. Shi and L. He , \"Variability-Aware Parametric Yield Estimation for Analog\/Mixed-Signal Circuits: Concepts, Algorithm, and Challenges,\" IEEE Design and Test , Vol. 31 , Issue 4 , pp. 6 -- 15 , Aug 2014 . F. Gong, H. Yu, Y. Shi and L. He, \"Variability-Aware Parametric Yield Estimation for Analog\/Mixed-Signal Circuits: Concepts, Algorithm, and Challenges,\" IEEE Design and Test, Vol. 31, Issue 4, pp. 6--15, Aug 2014.","journal-title":"\"Variability-Aware Parametric Yield Estimation for Analog\/Mixed-Signal Circuits: Concepts, Algorithm, and Challenges,\" IEEE Design and Test"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"e_1_3_2_1_8_1","volume-title":"Automation & Test in Europe Conference & Exhibition","author":"R\u00e9mond E.","year":"2011","unstructured":"E. R\u00e9mond , E. Nercessian , C. Bernicot and R. Mina , \" Mathematical approach based on a \"Design of Experiment\" to simulate process variation,\" in Design , Automation & Test in Europe Conference & Exhibition , 2011 . E. R\u00e9mond, E. Nercessian, C. Bernicot and R. Mina, \"Mathematical approach based on a \"Design of Experiment\" to simulate process variation,\" in Design, Automation & Test in Europe Conference & Exhibition, 2011."},{"key":"e_1_3_2_1_9_1","volume-title":"Statistical Analysis of 6T SRAM Data Retention Voltage under Process Variation,\" in IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","author":"Vatajelu E. I.","year":"2011","unstructured":"E. I. Vatajelu and J. Figueras , \" Statistical Analysis of 6T SRAM Data Retention Voltage under Process Variation,\" in IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) , 2011 . E. I. Vatajelu and J. Figueras, \"Statistical Analysis of 6T SRAM Data Retention Voltage under Process Variation,\" in IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011."},{"key":"e_1_3_2_1_10_1","volume-title":"Using ECC and Redundancy to minimize VMIN induced Yield Loss in 6T SRAM Arrays,\" in IEEE International Conference on IC Design & Technology (ICICDT)","author":"Shamanna G.","year":"2012","unstructured":"G. Shamanna , R. Gaurav , Raghavendra, Y. K, P. Marfatia and B. Kshatri , \" Using ECC and Redundancy to minimize VMIN induced Yield Loss in 6T SRAM Arrays,\" in IEEE International Conference on IC Design & Technology (ICICDT) , 2012 . G. Shamanna, R. Gaurav, Raghavendra, Y. K, P. Marfatia and B. Kshatri, \"Using ECC and Redundancy to minimize VMIN induced Yield Loss in 6T SRAM Arrays,\" in IEEE International Conference on IC Design & Technology (ICICDT), 2012."}],"event":{"name":"GLSVLSI '16: Great Lakes Symposium on VLSI 2016","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Boston Massachusetts USA","acronym":"GLSVLSI '16"},"container-title":["Proceedings of the 26th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2903005","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2902961.2903005","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:39:03Z","timestamp":1750221543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2903005"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,18]]},"references-count":10,"alternative-id":["10.1145\/2902961.2903005","10.1145\/2902961"],"URL":"https:\/\/doi.org\/10.1145\/2902961.2903005","relation":{},"subject":[],"published":{"date-parts":[[2016,5,18]]},"assertion":[{"value":"2016-05-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}