{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:29Z","timestamp":1750306289631,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":8,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,5,18]],"date-time":"2016-05-18T00:00:00Z","timestamp":1463529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"publisher","award":["TEC2013-45638-C3-2-R"],"award-info":[{"award-number":["TEC2013-45638-C3-2-R"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,5,18]]},"DOI":"10.1145\/2902961.2903006","type":"proceedings-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T18:21:10Z","timestamp":1463163670000},"page":"381-384","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["ASIC Implementation of An All-digital Self-adaptive PVTA Variation-aware Clock Generation System"],"prefix":"10.1145","author":[{"given":"Jordi","family":"P\u00e9rez-Puigdemont","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}]},{"given":"Francesc","family":"Moll","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2016,5,18]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"issue":"1","key":"e_1_3_2_1_2_1","first-page":"194","article-title":"nm resilient microprocessor core for dynamic variation tolerance. Solid-State Circuits","volume":"46","author":"Bowman K.","year":"2011","unstructured":"K. Bowman , J. Tschanz , S. Lu , P. Aseron , M. Khellah , A. Raychowdhury , B. Geuskens , C. Tokunaga , C. Wilkerson , T. Karnik , and V. De . A 45 nm resilient microprocessor core for dynamic variation tolerance. Solid-State Circuits , IEEE Journal of , 46 ( 1 ): 194 -- 208 , Jan 2011 . K. Bowman, J. Tschanz, S. Lu, P. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, C. Tokunaga, C. Wilkerson, T. Karnik, and V. De. A 45 nm resilient microprocessor core for dynamic variation tolerance. Solid-State Circuits, IEEE Journal of, 46(1):194--208, Jan 2011.","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2008.4567288"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155622"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/VARI.2014.6957084"},{"issue":"2","key":"e_1_3_2_1_7_1","first-page":"90","article-title":"All-digital simple clock synthesis through a glitch-free variable-length ring oscillator. Circuits and Systems II: Express Briefs","volume":"61","author":"Perez-Puigdemont J.","year":"2014","unstructured":"J. Perez-Puigdemont , F. Moll , and A. Calomarde . All-digital simple clock synthesis through a glitch-free variable-length ring oscillator. Circuits and Systems II: Express Briefs , IEEE Transactions on , 61 ( 2 ): 90 -- 94 , Feb 2014 . J. Perez-Puigdemont, F. Moll, and A. Calomarde. All-digital simple clock synthesis through a glitch-free variable-length ring oscillator. Circuits and Systems II: Express Briefs, IEEE Transactions on, 61(2):90--94, Feb 2014.","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2149531"}],"event":{"name":"GLSVLSI '16: Great Lakes Symposium on VLSI 2016","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Boston Massachusetts USA","acronym":"GLSVLSI '16"},"container-title":["Proceedings of the 26th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2903006","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2902961.2903006","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:39:03Z","timestamp":1750221543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2903006"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,18]]},"references-count":8,"alternative-id":["10.1145\/2902961.2903006","10.1145\/2902961"],"URL":"https:\/\/doi.org\/10.1145\/2902961.2903006","relation":{},"subject":[],"published":{"date-parts":[[2016,5,18]]},"assertion":[{"value":"2016-05-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}