{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:29Z","timestamp":1750306289049,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":12,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,5,18]],"date-time":"2016-05-18T00:00:00Z","timestamp":1463529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,5,18]]},"DOI":"10.1145\/2902961.2903019","type":"proceedings-article","created":{"date-parts":[[2016,5,13]],"date-time":"2016-05-13T18:21:10Z","timestamp":1463163670000},"page":"251-256","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices"],"prefix":"10.1145","author":[{"given":"Yu","family":"Bai","sequence":"first","affiliation":[{"name":"University of Central Florida, Orlando, FL, USA"}]},{"given":"Bo","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Central Florida, orlando, FL, USA"}]},{"given":"Weidong","family":"Kuang","sequence":"additional","affiliation":[{"name":"The University of Texas Rio Grande Valley, Edinburg, TX, USA"}]},{"given":"Mingjie","family":"Lin","sequence":"additional","affiliation":[{"name":"University of Central Florida, orlando, FL, USA"}]}],"member":"320","published-online":{"date-parts":[[2016,5,18]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9780511674730","volume-title":"A Designer's Guide to Asynchronous VLSI","author":"Beerel P. A.","year":"2010","unstructured":"P. A. Beerel , R. O. Ozdag , and M. Ferretti . A Designer's Guide to Asynchronous VLSI . Cambridge University Press , New York, NY, USA , 1 st edition, 2010 . P. A. Beerel, R. O. Ozdag, and M. Ferretti. A Designer's Guide to Asynchronous VLSI. Cambridge University Press, New York, NY, USA, 1st edition, 2010.","edition":"1"},{"issue":"12","key":"e_1_3_2_1_2_1","first-page":"957","article-title":"Low-power asynchronous ncl pipelines with fine-grain power gating and early sleep. Circuits and Systems II: Express Briefs","volume":"61","author":"Chang M.-C.","year":"2014","unstructured":"M.-C. Chang , M.-H. Hsieh , and P.-H. Yang . Low-power asynchronous ncl pipelines with fine-grain power gating and early sleep. Circuits and Systems II: Express Briefs , IEEE Transactions on , 61 ( 12 ): 957 -- 961 , Dec 2014 . M.-C. Chang, M.-H. Hsieh, and P.-H. Yang. Low-power asynchronous ncl pipelines with fine-grain power gating and early sleep. Circuits and Systems II: Express Briefs, IEEE Transactions on, 61(12):957--961, Dec 2014.","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_3_1","volume-title":"Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing. arXiv preprint arXiv:1402.2902","author":"Fan D.","year":"2014","unstructured":"D. Fan , M. Sharad , A. Sengupta , and K. Roy . Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing. arXiv preprint arXiv:1402.2902 , 2014 . D. Fan, M. Sharad, A. Sengupta, and K. Roy. Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing. arXiv preprint arXiv:1402.2902, 2014."},{"key":"e_1_3_2_1_4_1","volume-title":"STT-SNN: A spin-transfer-torque based soft-limiting non-linear neuron for low-power artificial neural networks. CoRR, abs\/1412.8648","author":"Shim Y.","year":"2014","unstructured":". Fan, Y. Shim , A. Raghunathan , and K. Roy . STT-SNN: A spin-transfer-torque based soft-limiting non-linear neuron for low-power artificial neural networks. CoRR, abs\/1412.8648 , 2014 .. . Fan, Y. Shim, A. Raghunathan, and K. Roy. STT-SNN: A spin-transfer-torque based soft-limiting non-linear neuron for low-power artificial neural networks. CoRR, abs\/1412.8648, 2014.."},{"key":"e_1_3_2_1_5_1","first-page":"51","volume-title":"Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on","author":"Gupta S.","year":"2011","unstructured":". Fong, S. Gupta , N. Mojumder , S. Choday , C. Augustine , and K. Roy . Knack: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque mram bit-cells . In Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on , pages 51 -- 54 , Sept 2011 . . Fong, S. Gupta, N. Mojumder, S. Choday, C. Augustine, and K. Roy. Knack: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque mram bit-cells. In Simulation of Semiconductor Processes and Devices (SISPAD), 2011 International Conference on, pages 51--54, Sept 2011."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724553"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.24"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2012.151"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/785166.785308"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2231889"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2003.12.004"},{"key":"e_1_3_2_1_12_1","volume-title":"Perpendicular-magnetic-anisotropy cofeb racetrack memory. Journal of Applied Physics, 111(9)","author":"Zhang Y.","year":"2012","unstructured":"Y. Zhang , W. S. Zhao , D. Ravelosona , J.-O. Klein , J. V. Kim , and C. Chappert . Perpendicular-magnetic-anisotropy cofeb racetrack memory. Journal of Applied Physics, 111(9) :, 2012 . Y. Zhang, W. S. Zhao, D. Ravelosona, J.-O. Klein, J. V. Kim, and C. Chappert. Perpendicular-magnetic-anisotropy cofeb racetrack memory. Journal of Applied Physics, 111(9):, 2012."}],"event":{"name":"GLSVLSI '16: Great Lakes Symposium on VLSI 2016","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Boston Massachusetts USA","acronym":"GLSVLSI '16"},"container-title":["Proceedings of the 26th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2903019","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2902961.2903019","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:39:03Z","timestamp":1750221543000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2902961.2903019"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,18]]},"references-count":12,"alternative-id":["10.1145\/2902961.2903019","10.1145\/2902961"],"URL":"https:\/\/doi.org\/10.1145\/2902961.2903019","relation":{},"subject":[],"published":{"date-parts":[[2016,5,18]]},"assertion":[{"value":"2016-05-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}