{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:11:16Z","timestamp":1750306276104,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,3,4]],"date-time":"2016-03-04T00:00:00Z","timestamp":1457049600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,3,4]]},"DOI":"10.1145\/2905055.2905321","type":"proceedings-article","created":{"date-parts":[[2016,8,26]],"date-time":"2016-08-26T12:40:09Z","timestamp":1472215209000},"page":"1-5","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Low-Power High Speed 1-bit Full Adder Circuit Design"],"prefix":"10.1145","author":[{"given":"Shailesh","family":"Dwivedi","sequence":"first","affiliation":[{"name":"Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India"}]},{"given":"Kavita","family":"Khare","sequence":"additional","affiliation":[{"name":"Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India"}]},{"given":"Ajay Kumar","family":"Dadoria","sequence":"additional","affiliation":[{"name":"Department of electronics and communication, Maulana Azad National Institute of Technology, Bhopal, India"}]}],"member":"320","published-online":{"date-parts":[[2016,3,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.386232"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.988727"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.808446"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.84935"},{"volume-title":"MA: Kluwer","year":"1995","author":"Chandrakasan A. P.","key":"e_1_3_2_1_5_1"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.403712"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.597298"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2013.05.001"},{"key":"e_1_3_2_1_9_1","first-page":"74","article-title":"Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits","volume":"6","author":"Uma R.","year":"2012","journal-title":"Proc. Of ICCCS"},{"volume-title":"20th Iranian Conf. Electrical Engineering, (ICEE2012)","year":"2012","author":"Asmangerdi Nabiallah Shiri","key":"e_1_3_2_1_10_1"},{"key":"e_1_3_2_1_11_1","first-page":"317","volume-title":"IEEE Int. Symp. Circuits Syst.","author":"Zhang M.","year":"2003"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887807"},{"volume-title":"IEEE Conf. Signal Processing and Int. Networks.","year":"2014","author":"Agarwal Mayur","key":"e_1_3_2_1_13_1"},{"issue":"10","key":"e_1_3_2_1_14_1","article-title":"Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit","volume":"23","author":"Bhattacharyya Partha","year":"2015","journal-title":"IEEE Trans. Very Large Scale Intsgr. (VLSI) Syst."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20010170"},{"volume-title":"World Congress on Information and Communication Technologies.","year":"2012","author":"Shrivas Jayram","key":"e_1_3_2_1_16_1"}],"event":{"name":"ICTCS '16: Second International Conference on Information and Communication Technology for Competitive Strategies","acronym":"ICTCS '16","location":"Udaipur India"},"container-title":["Proceedings of the Second International Conference on Information and Communication Technology for Competitive Strategies"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2905055.2905321","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2905055.2905321","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:38:46Z","timestamp":1750221526000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2905055.2905321"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,3,4]]},"references-count":16,"alternative-id":["10.1145\/2905055.2905321","10.1145\/2905055"],"URL":"https:\/\/doi.org\/10.1145\/2905055.2905321","relation":{},"subject":[],"published":{"date-parts":[[2016,3,4]]},"assertion":[{"value":"2016-03-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}