{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:48:48Z","timestamp":1750308528245,"version":"3.41.0"},"reference-count":36,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2016,5,27]],"date-time":"2016-05-27T00:00:00Z","timestamp":1464307200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100012190","name":"Ministry of Science and Higher Education","doi-asserted-by":"crossref","award":["8686\/E-367\/S\/2015"],"award-info":[{"award-number":["8686\/E-367\/S\/2015"]}],"id":[{"id":"10.13039\/501100012190","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2017,1,31]]},"abstract":"<jats:p>The logic synthesis of ultra-high-speed FSMs is presented. The state assignment is based on a well-known method that uses output vectors. This technique is adjusted to include elements of two-level minimization and takes into account the limited number of terms contained in the programmable-AND\/fixed-OR logic cell. The state assignment is based on a special form of the binary decision tree. The second phase of the FSM design is logic optimization. The optimization method is based on tristate buffers, thus making possible a one-logic-level FSM structure. The key point is to search partition variables that control the tristate buffers. This technique can also be applied to combinational circuits or the output block of FSMs only.<\/jats:p>\n          <jats:p>Algorithms for state assignment and optimization are presented and richly illustrated by examples. The method is dedicated to using specific features of complex programmable logic devices. Experimental results prove its effectiveness (e.g., the implementation of the the 16-bit counter requires 136 logic cells and one-logic-cell level instead of 213 cells and four levels). The optimization method using tristate buffers and a state assignment binary decision tree can be directly applied to FPGA-dedicated logic synthesis.<\/jats:p>","DOI":"10.1145\/2905366","type":"journal-article","created":{"date-parts":[[2016,5,31]],"date-time":"2016-05-31T12:15:09Z","timestamp":1464696909000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers"],"prefix":"10.1145","volume":"22","author":[{"given":"Robert","family":"Czerwinski","sequence":"first","affiliation":[{"name":"Silesian University of Technology, Gliwice, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dariusz","family":"Kania","sequence":"additional","affiliation":[{"name":"Silesian University of Technology, Gliwice, Poland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,5,27]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"Altera. 2004. APEX 20K Programmable Logic Device Family. Data Sheet ver. 5.1.  Altera. 2004. APEX 20K Programmable Logic Device Family. Data Sheet ver. 5.1."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277220"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126614500868"},{"key":"e_1_2_1_4_1","doi-asserted-by":"crossref","unstructured":"R. Brayton G. Hachtel C. McMullen and A. Sangiovanni-Vincentelli. 1984. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Boston.   R. Brayton G. Hachtel C. McMullen and A. Sangiovanni-Vincentelli. 1984. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Boston.","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.2478\/v10177-012-0005-7"},{"volume-title":"IEEE International Conference on Field-Programmable Technology. 204--210","author":"Chen S. L.","key":"e_1_2_1_6_1","unstructured":"S. L. Chen , T. T. Hwang , and C. L. Liu . 2002. A technology mapping algorithm for CPLD architectures . In IEEE International Conference on Field-Programmable Technology. 204--210 . S. L. Chen, T. T. Hwang, and C. L. Liu. 2002. A technology mapping algorithm for CPLD architectures. In IEEE International Conference on Field-Programmable Technology. 204--210."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.2478\/v10006-009-0052-0"},{"key":"e_1_2_1_8_1","doi-asserted-by":"crossref","unstructured":"R. Czerwinski and D. Kania. 2010. A synthesis of high speed finite state machines. Bulletin of the Polish Academy of Sciences\u2014Technical Sciences 58 4 (2010) 635--643.  R. Czerwinski and D. Kania. 2010. A synthesis of high speed finite state machines. Bulletin of the Polish Academy of Sciences\u2014Technical Sciences 58 4 (2010) 635--643.","DOI":"10.2478\/v10175-010-0067-6"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2011.06.004"},{"key":"e_1_2_1_10_1","doi-asserted-by":"crossref","unstructured":"R. Czerwinski and D. Kania. 2013. Finite State Machine Logic Synthesis for Complex Programmable Logic Devices. Springer-Verlag Berlin.   R. Czerwinski and D. Kania. 2013. Finite State Machine Logic Synthesis for Complex Programmable Logic Devices. Springer-Verlag Berlin.","DOI":"10.1007\/978-3-642-36166-1"},{"volume-title":"Synthesis and Optimization of Digital Circuits","author":"De Micheli G.","key":"e_1_2_1_11_1","unstructured":"G. De Micheli . 1994. Synthesis and Optimization of Digital Circuits . McGraw-Hill , New York . G. De Micheli. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1093\/ietisy\/e88-d.7.1492"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.2002"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.62788"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.2478\/v10006-007-0011-6"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1134\/S1064230714010067"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126692000027"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:19990639"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.2000.874626"},{"volume-title":"Proceedings of the International Conference on VLSI. 187--206","author":"Lin B.","key":"e_1_2_1_20_1","unstructured":"B. Lin and R. Newton . 1989. Synthesis of multiple level logic from symbolic high-level description languages . In Proceedings of the International Conference on VLSI. 187--206 . B. Lin and R. Newton. 1989. Synthesis of multiple level logic from symbolic high-level description languages. In Proceedings of the International Conference on VLSI. 187--206."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923245"},{"key":"e_1_2_1_22_1","volume-title":"Minimization of boolean functions. The Bell System Technical Journal 35 (November","author":"McCluskey E.","year":"1956","unstructured":"E. McCluskey . 1956. Minimization of boolean functions. The Bell System Technical Journal 35 (November 1956 ), 1417--1444. E. McCluskey. 1956. Minimization of boolean functions. The Bell System Technical Journal 35 (November 1956), 1417--1444."},{"key":"e_1_2_1_23_1","unstructured":"MCNC. 1991. LGSynth\u201991 benchmarks. Collaborative Benchmarking Laboratory Department of Computer Science at North Carolina State University. Retrieved from http:\/\/www.cbl.ncsu.edu:16080\/benchmarks\/ LGSynth91\/.  MCNC. 1991. LGSynth\u201991 benchmarks. Collaborative Benchmarking Laboratory Department of Computer Science at North Carolina State University. Retrieved from http:\/\/www.cbl.ncsu.edu:16080\/benchmarks\/ LGSynth91\/."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20052307"},{"volume-title":"Binary Decision Diagrams and Applications for VLSI CAD","author":"Minato S.","key":"e_1_2_1_25_1","unstructured":"S. Minato . 1996. Binary Decision Diagrams and Applications for VLSI CAD . Kluwer Academic Publishers , Dordrecht . S. Minato. 1996. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, Dordrecht."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1080\/00029890.1952.11988183"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.277632"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.5555\/876894.880890"},{"key":"e_1_2_1_29_1","unstructured":"T. Sasao and M. Perkowski. 1993. EXOR Logic Synthesis. Kluwer Dordrecht.  T. Sasao and M. Perkowski. 1993. EXOR Logic Synthesis. Kluwer Dordrecht."},{"volume-title":"Proceedings of the International Conference on Computer Design (ICCD\u201992)","author":"Sentovich E.","key":"e_1_2_1_30_1","unstructured":"E. Sentovich , K. Singh , L. Lavagno , C. Moon , R. Murgai , A. Saldanha , H. Savoj , P. Stephan , R. Brayton , and A. Sangiovanni-Vincentelli . 1992. SIS: A system for sequential circuit synthesis . In Proceedings of the International Conference on Computer Design (ICCD\u201992) . 328--333. E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. 1992. SIS: A system for sequential circuit synthesis. In Proceedings of the International Conference on Computer Design (ICCD\u201992). 328--333."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1949.tb03624.x"},{"volume-title":"PLDs, CPLDs, & FPGAs","author":"Sharma K.","key":"e_1_2_1_32_1","unstructured":"K. Sharma . 1998. Programmable Logic Handbook , PLDs, CPLDs, & FPGAs . McGraw-Hill , New York . K. Sharma. 1998. Programmable Logic Handbook, PLDs, CPLDs, & FPGAs. McGraw-Hill, New York."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.644031"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.59068"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.2478\/v10006-011-0030-1"},{"key":"e_1_2_1_36_1","unstructured":"Xilinx. 2007. Virtex-II Platform FPGAs: Complete Data Sheet.  Xilinx. 2007. Virtex-II Platform FPGAs: Complete Data Sheet."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2905366","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2905366","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T18:55:49Z","timestamp":1750272949000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2905366"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5,27]]},"references-count":36,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2017,1,31]]}},"alternative-id":["10.1145\/2905366"],"URL":"https:\/\/doi.org\/10.1145\/2905366","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2016,5,27]]},"assertion":[{"value":"2015-08-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-05-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}