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Taking a heat conduction simulation and an FDTD electromagnetic field simulation as benchmark applications, powerperformance profiling results are presented focusing on the effect of high-level pipeline parameters. As a result, it is shown that the optimal power efficiency can be achieved basically by optimizing the execution performance. The relationship between power efficiency and the clock frequency is also discussed.<\/jats:p>","DOI":"10.1145\/2927964.2927967","type":"journal-article","created":{"date-parts":[[2016,4,25]],"date-time":"2016-04-25T19:51:13Z","timestamp":1461613873000},"page":"9-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization"],"prefix":"10.1145","volume":"43","author":[{"given":"Koji","family":"Okina","sequence":"first","affiliation":[{"name":"Nagasaki University, Japan"}]},{"given":"Rie","family":"Soejima","sequence":"additional","affiliation":[{"name":"Nagasaki University, Japan"}]},{"given":"Kota","family":"Fukumoto","sequence":"additional","affiliation":[{"name":"Nagasaki University, Japan"}]},{"given":"Yuichiro","family":"Shibata","sequence":"additional","affiliation":[{"name":"Nagasaki University, Japan"}]},{"given":"Kiyoshi","family":"Oguri","sequence":"additional","affiliation":[{"name":"Nagasaki University, Japan"}]}],"member":"320","published-online":{"date-parts":[[2016,4,22]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Editor","author":"Peter K.","year":"2008","unstructured":"K. Peter , Editor and Study Lead, \"ExaScale Computing Study : Technology Challenges in Achieving Exascale Systems ,\" 2008 . K. Peter, Editor and Study Lead, \"ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems,\" 2008."},{"key":"e_1_2_1_2_1","first-page":"67","article-title":"System-Level Techniques for Estimating and Reducing Energy Consumption in Real-Time Embedded Systems","author":"Ishihara T.","year":"2007","unstructured":"T. Ishihara and M. Goudarzi , \" System-Level Techniques for Estimating and Reducing Energy Consumption in Real-Time Embedded Systems ,\" International Soc Design Conference , pp. 67 -- 72 , 2007 . T. Ishihara and M. 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Sano, \"FPGA-Based Systolic Computational-Memory Array for Scalable Stencil Computations,\" in High-Performance Computing Using FPGAs (W. Vanderbauwhede and K. Benkrid, eds.), pp. 279--303, Springer New York, 2013."},{"key":"e_1_2_1_6_1","doi-asserted-by":"crossref","unstructured":"T.\n      Kobori\n     and \n      T.\n      Maruyama \"\n  A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA \" in Field Programmable Logic and Application\n   (P. Cheung and G. Constantinides eds.) vol. \n  2778\n   of \n  Lecture Notes in Computer Science pp. \n  755\n  --\n  765 Springer 2003\n  .  T. Kobori and T. Maruyama \"A High Speed Computation System for 3D FCHC Lattice Gas Model with FPGA \" in Field Programmable Logic and Application (P. Cheung and G. Constantinides eds.) vol. 2778 of Lecture Notes in Computer Science pp. 755--765 Springer 2003.","DOI":"10.1007\/978-3-540-45234-8_73"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2693714.2693727"},{"key":"e_1_2_1_8_1","unstructured":"Impulse Accelerated Technologies \"Impulse C.\" http:\/\/www.impulseaccelerated.com\/.{9} Xilinx \"Vivado HLS Design.\" http:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design\/index.html.  Impulse Accelerated Technologies \"Impulse C.\" http:\/\/www.impulseaccelerated.com\/.{9} Xilinx \"Vivado HLS Design.\" http:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design\/index.html."},{"key":"e_1_2_1_9_1","first-page":"1","volume-title":"2013 International Conference on","author":"Dohi K.","year":"2013","unstructured":"K. Dohi , K. Fukumoto , Y. Shibata , and K. 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