{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,5]],"date-time":"2026-02-05T07:13:09Z","timestamp":1770275589037,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,8,8]],"date-time":"2016-08-08T00:00:00Z","timestamp":1470614400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,8,8]]},"DOI":"10.1145\/2934583.2934607","type":"proceedings-article","created":{"date-parts":[[2016,7,29]],"date-time":"2016-07-29T14:51:46Z","timestamp":1469803906000},"page":"130-135","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines"],"prefix":"10.1145","author":[{"given":"Monodeep","family":"Kar","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arvind","family":"Singh","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanu","family":"Mathew","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anand","family":"Rajan","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[{"name":"Intel Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saibal","family":"Mukhopadhyay","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,8,8]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Proc. Int'l Cryptology Conf. (CRYPTO)","author":"Kocher P.","year":"1999"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"E. Brier etal \"Correlation Power Analysis with a Leakage Model \" CHES 2004.  E. Brier et al. \"Correlation Power Analysis with a Leakage Model \" CHES 2004.","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"e_1_3_2_1_3_1","unstructured":"K. Tiri etal \"A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation \" DATE 2004.   K. Tiri et al. \"A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation \" DATE 2004."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","unstructured":"M Rivain etal \"Provably Secure Higher-Order Masking of AES \" CHES 2010.   M Rivain et al. \"Provably Secure Higher-Order Masking of AES \" CHES 2010.","DOI":"10.1007\/978-3-642-15031-9_28"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"A. Shamir \"Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies \" CHES 2000.   A. Shamir \"Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies \" CHES 2000.","DOI":"10.1007\/3-540-44499-8_5"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"A. Gornik etal \"A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design Implementation and Evaluation \" in IEEE TCAD Aug. 2015.  A. Gornik et al. \"A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design Implementation and Evaluation \" in IEEE TCAD Aug. 2015.","DOI":"10.1109\/TCAD.2015.2423274"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"C. Tokunaga etal \"Secure AES engine with a local switched-capacitor current equalizer \" IEEE ISSCC 2009.  C. Tokunaga et al. \"Secure AES engine with a local switched-capacitor current equalizer \" IEEE ISSCC 2009.","DOI":"10.1109\/ISSCC.2009.4977309"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488830"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"A. Singh etal \"Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators \" IEEE\/ACM ISLPED 2015.  A. Singh et al. \"Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators \" IEEE\/ACM ISLPED 2015.","DOI":"10.1109\/ISLPED.2015.7273503"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"A. Uzun etal \"Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System \" in IEEE JETCAS June 2014.  A. Uzun et al. \"Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System \" in IEEE JETCAS June 2014.","DOI":"10.1109\/JETCAS.2014.2315880"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744866"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"M. Kar etal \"Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study \" IEEE CICC 2014.  M. Kar et al. \"Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study \" IEEE CICC 2014.","DOI":"10.1109\/CICC.2014.6946135"},{"key":"e_1_3_2_1_13_1","unstructured":"E. A. Burton etal \"FIVR - Fully integrated voltage regulators on 4th generation Intel\u00ae Core\u2122 SoCs \" IEEE APEC 2014.  E. A. Burton et al. \"FIVR - Fully integrated voltage regulators on 4th generation Intel\u00ae Core\u2122 SoCs \" IEEE APEC 2014."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"H. K. Krishnamurthy etal \"A 500 MHz 68% efficient fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS \" in VLSIC 2014  H. K. Krishnamurthy et al. \"A 500 MHz 68% efficient fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS \" in VLSIC 2014","DOI":"10.1109\/VLSIC.2014.6858438"},{"key":"e_1_3_2_1_15_1","unstructured":"A. M. Rahimi etal \"Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier\" IR App. Note.  A. M. Rahimi et al. \"Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier\" IR App. Note."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"O. Meynard etal \"Characterization of the Electromagnetic Side Channel in Frequency Domain \" INSCRYPT 2010 O. Meynard et al. \"Characterization of the Electromagnetic Side Channel in Frequency Domain \" INSCRYPT 2010","DOI":"10.1007\/978-3-642-21518-6_33"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"M. Nassar etal \"RSM: a Small and Fast Countermeasure for AES Secure against 1st and 2nd-order Zero-Offset SCAs\" in DATE 2012   M. Nassar et al. \"RSM: a Small and Fast Countermeasure for AES Secure against 1st and 2nd-order Zero-Offset SCAs\" in DATE 2012","DOI":"10.1109\/DATE.2012.6176671"}],"event":{"name":"ISLPED '16: International Symposium on Low Power Electronics and Design","location":"San Francisco Airport CA USA","acronym":"ISLPED '16","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2016 International Symposium on Low Power Electronics and Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2934583.2934607","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2934583.2934607","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:56:19Z","timestamp":1750222579000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2934583.2934607"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,8,8]]},"references-count":17,"alternative-id":["10.1145\/2934583.2934607","10.1145\/2934583"],"URL":"https:\/\/doi.org\/10.1145\/2934583.2934607","relation":{},"subject":[],"published":{"date-parts":[[2016,8,8]]},"assertion":[{"value":"2016-08-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}