{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,5]],"date-time":"2026-08-05T08:24:46Z","timestamp":1785918286403,"version":"3.56.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,8,8]],"date-time":"2016-08-08T00:00:00Z","timestamp":1470614400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100007601","name":"Horizon 2020","doi-asserted-by":"publisher","award":["687973"],"award-info":[{"award-number":["687973"]}],"id":[{"id":"10.13039\/501100007601","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,8,8]]},"DOI":"10.1145\/2934583.2934629","type":"proceedings-article","created":{"date-parts":[[2016,7,29]],"date-time":"2016-07-29T14:51:46Z","timestamp":1469803906000},"page":"236-241","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches"],"prefix":"10.1145","author":[{"given":"Fabian","family":"Oboril","sequence":"first","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT)"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fazal","family":"Hameed","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT)"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rajendra","family":"Bishnoi","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT)"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ali","family":"Ahari","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT)"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Helia","family":"Naeimi","sequence":"additional","affiliation":[{"name":"Intel Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mehdi","family":"Tahoori","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology (KIT)"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2016,8,8]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357091"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835944"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/2016802.2016848"},{"key":"e_1_3_2_1_4_1","volume-title":"ISCA","author":"Alameldeen A.","year":"2004","unstructured":"A. Alameldeen and D. Wood . Adaptive Cache Compression for High-performance Processors . In ISCA , 2004 . A. Alameldeen and D. Wood. Adaptive Cache Compression for High-performance Processors. In ISCA, 2004."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.82"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2014.6783375"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020989"},{"key":"e_1_3_2_1_8_1","volume-title":"DATE","author":"Chen Y. T.","year":"2012","unstructured":"Y. T. Chen Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design . In DATE , 2012 . Y. T. Chen et al. Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design. In DATE, 2012."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542288"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.6"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228406"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/1206691"},{"key":"e_1_3_2_1_14_1","volume-title":"ISQED","author":"Jung J.","year":"2013","unstructured":"J. Jung , Y. Nakata , M. Yoshimoto , and H. Kawaguchi . Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-zero-data Flags . In ISQED , 2013 . J. Jung, Y. Nakata, M. Yoshimoto, and H. Kawaguchi. Energy-Efficient Spin-Transfer Torque RAM Cache Exploiting Additional All-zero-data Flags. In ISQED, 2013."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155670"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081375"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750417"},{"key":"e_1_3_2_1_19_1","volume-title":"Microelectronics","author":"Mejdoubi A.","year":"2012","unstructured":"A. Mejdoubi , G. Prenat , and B. Dieny . A compact model of precessional spin-transfer switching for MTJ with a perpendicular polarizer . In Microelectronics , 2012 . A. Mejdoubi, G. Prenat, and B. Dieny. A compact model of precessional spin-transfer switching for MTJ with a perpendicular polarizer. In Microelectronics, 2012."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000074"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540715"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2723165"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360150"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1880037.1880040"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2496363"}],"event":{"name":"ISLPED '16: International Symposium on Low Power Electronics and Design","location":"San Francisco Airport CA USA","acronym":"ISLPED '16","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2016 International Symposium on Low Power Electronics and Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2934583.2934629","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2934583.2934629","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:56:19Z","timestamp":1750222579000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2934583.2934629"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,8,8]]},"references-count":29,"alternative-id":["10.1145\/2934583.2934629","10.1145\/2934583"],"URL":"https:\/\/doi.org\/10.1145\/2934583.2934629","relation":{},"subject":[],"published":{"date-parts":[[2016,8,8]]},"assertion":[{"value":"2016-08-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}