{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:46:11Z","timestamp":1761648371376,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,8,8]],"date-time":"2016-08-08T00:00:00Z","timestamp":1470614400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,8,8]]},"DOI":"10.1145\/2934583.2934633","type":"proceedings-article","created":{"date-parts":[[2016,7,29]],"date-time":"2016-07-29T14:51:46Z","timestamp":1469803906000},"page":"260-265","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["FVCAG"],"prefix":"10.1145","author":[{"given":"Arun","family":"Joseph","sequence":"first","affiliation":[{"name":"IBM Systems Group, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Spandana","family":"Rachamalla","sequence":"additional","affiliation":[{"name":"IBM Systems Group, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rahul M.","family":"Rao","sequence":"additional","affiliation":[{"name":"IBM Systems Group, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anand","family":"Haridass","sequence":"additional","affiliation":[{"name":"IBM Systems Group, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pradeep K.","family":"Nalla","sequence":"additional","affiliation":[{"name":"IBM Systems Group, Bangalore, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,8,8]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Liberty Reference Manual Sep. 2008 Version 2008.09.  Liberty Reference Manual Sep. 2008 Version 2008.09."},{"volume-title":"IEEE","year":"2003","key":"e_1_3_2_1_2_1","unstructured":"1603-2003VIEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks , IEEE , 2003 . 1603-2003VIEEE Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks, IEEE, 2003."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/2561828.2561918"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/240518.240601"},{"key":"e_1_3_2_1_5_1","volume-title":"DAC","author":"Dhanwada N.","year":"2015","unstructured":"Dhanwada , N. , 2015 . A Hybrid Approach to Standard Cell Power Characterization based on PVT Independent Contributor Modeling for use in Traditional Power Analysis Flows , DAC 2015. Dhanwada, N., et al. 2015. A Hybrid Approach to Standard Cell Power Characterization based on PVT Independent Contributor Modeling for use in Traditional Power Analysis Flows, DAC 2015."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339659"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627619"},{"issue":"1","key":"e_1_3_2_1_9_1","first-page":"10","volume":"50","author":"Fluhr E.J.","year":"2015","unstructured":"Fluhr , E.J. ; Baumgartner , S. ; Boerstler , D. ; Bulzacchelli , J.F. ; Diemoz , T. ; Dreps , D. ; English , G. ; Friedrich , J. ; Gattiker , A. ; Gloekler , T. ; Gonzalez , C. ; Hibbeler , J.D. ; Jenkins , K.A. ; Yong Kim ; Muench, P.; Nett , R. ; Paredes , J. ; Pille , J. ; Plass , D. ; Restle , P. ; Robertazzi , R. ; Shan , D. ; Siljenberg , D. ; Sperling , M. ; Stawiasz , K. ; Still , G. ; Toprak-Deniz , Z. ; Warnock , J. ; Wiedemeier , G. ; Zyuban , V. , \" The 12-Core POWER8\u2122 Processor With 7.6 Tb\/s IO Bandwidth , Integrated Voltage Regulation, and Resonant Clocking ,\" in Solid-State Circuits , IEEE Journal of , vol. 50 , no. 1 , pp. 10 -- 23 , Jan. 2015 Fluhr, E.J.; Baumgartner, S.; Boerstler, D.; Bulzacchelli, J.F.; Diemoz, T.; Dreps, D.; English, G.; Friedrich, J.; Gattiker, A.; Gloekler, T.; Gonzalez, C.; Hibbeler, J.D.; Jenkins, K.A.; Yong Kim; Muench, P.; Nett, R.; Paredes, J.; Pille, J.; Plass, D.; Restle, P.; Robertazzi, R.; Shan, D.; Siljenberg, D.; Sperling, M.; Stawiasz, K.; Still, G.; Toprak-Deniz, Z.; Warnock, J.; Wiedemeier, G.; Zyuban, V., \"The 12-Core POWER8\u2122 Processor With 7.6 Tb\/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking,\" in Solid-State Circuits, IEEE Journal of, vol.50, no.1, pp. 10--23, Jan. 2015","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_10_1","volume-title":"Feb.","author":"Fluhr E.J.","year":"2014","unstructured":"Fluhr , E.J. , : A server-class processor in 22nm SOI with 7.6 Tb\/s off-chip bandwidth,\" In Proc. Int'l Solid State Circuits Conference (ISSCC) , Feb. 2014 . Fluhr, E.J., et al. \"POWER8: A server-class processor in 22nm SOI with 7.6 Tb\/s off-chip bandwidth,\" In Proc. Int'l Solid State Circuits Conference (ISSCC), Feb. 2014."},{"key":"e_1_3_2_1_11_1","unstructured":"Open Compute Project: http:\/\/www.opencompute.org\/  Open Compute Project: http:\/\/www.opencompute.org\/"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629957"},{"key":"e_1_3_2_1_13_1","volume-title":"VLSID 2016","author":"Pradeep Kumar Nalla","year":"2016","unstructured":"Pradeep Kumar Nalla , RajKumar Gajavelly, Ashutosh Misra and Hari Mony. 2016 . A Formal Method to Uncover Sequential Redundancy in an Industrial Context . VLSID 2016 Pradeep Kumar Nalla, RajKumar Gajavelly, Ashutosh Misra and Hari Mony. 2016. A Formal Method to Uncover Sequential Redundancy in an Industrial Context. VLSID 2016"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2006.12"},{"key":"e_1_3_2_1_15_1","volume-title":"Scalable Sequential Equivalence Checking across Arbitrary Design Transformations.\" International Conference on Computer Design","author":"Baumgartner H.","year":"2006","unstructured":"J. Baumgartner , H. Mony , V. Paruthi , R. Kanzelman and G. Janssen , \" Scalable Sequential Equivalence Checking across Arbitrary Design Transformations.\" International Conference on Computer Design , San Jose, CA . October 2006 . J. Baumgartner, H. Mony, V. Paruthi, R. Kanzelman and G. Janssen, \"Scalable Sequential Equivalence Checking across Arbitrary Design Transformations.\" International Conference on Computer Design, San Jose, CA. October 2006."},{"key":"e_1_3_2_1_16_1","first-page":"178","volume-title":"vol., no","author":"Warnock J.","year":"2010","unstructured":"Warnock , J. ; Sigal , L. ; Wendel , D. ; Muller , K.P. ; Friedrich , J. ; Zyuban , V. ; Cannon , E. ; KleinOsowski , A.J. , \"POWER7TM local clocking and clocked storage elements,\" in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International , vol., no ., pp. 178 -- 179 , 7-11 Feb. 2010 Warnock, J.; Sigal, L.; Wendel, D.; Muller, K.P.; Friedrich, J.; Zyuban, V.; Cannon, E.; KleinOsowski, A.J., \"POWER7TM local clocking and clocked storage elements,\" in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, vol., no., pp. 178--179, 7-11 Feb. 2010"}],"event":{"name":"ISLPED '16: International Symposium on Low Power Electronics and Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"San Francisco Airport CA USA","acronym":"ISLPED '16"},"container-title":["Proceedings of the 2016 International Symposium on Low Power Electronics and Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2934583.2934633","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2934583.2934633","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:56:19Z","timestamp":1750222579000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2934583.2934633"}},"subtitle":["A framework for formal verification driven power modeling and verification"],"short-title":[],"issued":{"date-parts":[[2016,8,8]]},"references-count":16,"alternative-id":["10.1145\/2934583.2934633","10.1145\/2934583"],"URL":"https:\/\/doi.org\/10.1145\/2934583.2934633","relation":{},"subject":[],"published":{"date-parts":[[2016,8,8]]},"assertion":[{"value":"2016-08-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}