{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T16:01:07Z","timestamp":1776441667386,"version":"3.51.2"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,9,17]],"date-time":"2017-09-17T00:00:00Z","timestamp":1505606400000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100006502","name":"Defense Sciences Office, DARPA","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006502","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CNS 18183"],"award-info":[{"award-number":["CNS 18183"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2016,9,17]]},"abstract":"<jats:p>\n                    This article proposes a rate-adaptive, two-tiered error-correction scheme (RATT-ECC) that provides strong reliability (10\n                    <jats:sup>10<\/jats:sup>\n                    <jats:italic toggle=\"yes\">x<\/jats:italic>\n                    reduction in raw FIT rate) for an HBM-like 3D DRAM system. The tier-1 code is a strong symbol-based code that can correct errors due to small granularity faults and detect errors caused by large granularity faults; the tier-2 code is an XOR-based code that corrects errors detected by the tier-1 code. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing reliability and timing performance.\n                  <\/jats:p>","DOI":"10.1145\/2957758","type":"journal-article","created":{"date-parts":[[2016,9,19]],"date-time":"2016-09-19T16:11:45Z","timestamp":1474301505000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["RATT-ECC"],"prefix":"10.1145","volume":"13","author":[{"given":"Hsing-Min","family":"Chen","sequence":"first","affiliation":[{"name":"Arizona State University, AZ, USA"}]},{"given":"Carole-Jean","family":"Wu","sequence":"additional","affiliation":[{"name":"Arizona State University, AZ, USA"}]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[{"name":"University of Michigan, MI, USA"}]},{"given":"Chaitali","family":"Chakrabarti","sequence":"additional","affiliation":[{"name":"Arizona State University, AZ, USA"}]}],"member":"320","published-online":{"date-parts":[[2016,9,17]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"May, 2013. http:\/\/developer.amd.com\/wordpress\/media\/2012\/10\/24593_APM_v21","author":"AMD.","year":"2011","unstructured":"AMD. 2011. AMD64 Architecture Programmer's Manual Volume 2: System Programming, May, 2013. http:\/\/developer.amd.com\/wordpress\/media\/2012\/10\/24593_APM_v21.pdf."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750408"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.33"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503215"},{"key":"e_1_2_1_5_1","unstructured":"HPArch. 2009. Macsim simulator. (2009). https:\/\/code.google.com\/p\/macsim\/downloads\/list."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","unstructured":"A. Hwang I. Stefanovici and B. Schroeder. 2012. Cosmic rays don\u2019t strike twice: Understanding the nature of DRAM errors and the implications for system design. SIGARCH Computer Architecture News 111--122. 10.1145\/2150976.2150989","DOI":"10.1145\/2150976.2150989"},{"key":"e_1_2_1_7_1","unstructured":"Intel. 2011. Intel xeon processor e7 family: Reliability availability and serviceability: Advanced data integrity and resiliency support for mission-critical deployment. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/white-papers\/xeon-e7-family-ras-server-paper.pdf."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485958"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485958"},{"key":"e_1_2_1_10_1","volume-title":"Symposium on VLSI Technology (VLSIT\u201912)","author":"Jeddeloh J.","unstructured":"J. Jeddeloh and B. Keeth. 2012. Hybrid memory cube new DRAM architecture increases density and performance. In Symposium on VLSI Technology (VLSIT\u201912). 87--88."},{"key":"e_1_2_1_11_1","unstructured":"JEDEC. 2010. DDR3 SDRAM specification. http:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD79-3E.pdf July 2010."},{"key":"e_1_2_1_12_1","volume-title":"JESD235. https:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD235A.pdf","author":"JEDEC HBM.","year":"2015","unstructured":"JEDEC HBM. 2013. High bandwidth memory (HBM) DRAM, JESD235. https:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD235A.pdf, Nov. 2015."},{"key":"e_1_2_1_13_1","volume-title":"IEEE International Test Conference (ITC\u201914)","author":"Jeon H.","unstructured":"H. Jeon, G. Loh, and M. Annavaram. 2014. Efficient RAS support for die-stacked DRAM. In IEEE International Test Conference (ITC\u201914). 1--10."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503243"},{"key":"e_1_2_1_15_1","volume-title":"Proceedings of the IEEE Southeastcon\u201996","author":"Joiner L. L.","unstructured":"L. L. Joiner and J. J. Komo. 1996. Time domain decoding of extended Reed-Solomon codes. In Proceedings of the IEEE Southeastcon\u201996. Bringing Together Education, Science and Technology. 238--241."},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1984.1096175"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817524"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2009.2023248"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","unstructured":"S. Lin and D. J. Costello. 2004. Error Control Coding (2nd ed.). Pearson New York.","DOI":"10.5555\/983680"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337161"},{"key":"e_1_2_1_21_1","volume-title":"Chipkill correct memory architecture","author":"Locklear D.","year":"2003","unstructured":"D. Locklear. 2000. Chipkill correct memory architecture. Dell Enterprise System Group. http:\/\/www.ece.umd.edu\/courses\/enee759h.S2003\/references\/chipkill.pdf, Aug. 2000."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_2_1_23_1","unstructured":"J. Meng D. Rossell and A. K. Coskun. 2011. 3D systems with on-chip DRAM for enabling low-power high-performance computing. In IEEE High Performance Embedded Computing HPEC."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.57"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2840807"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","unstructured":"T. R. Rao and E. Fujiwara. 1989. Error-Control Coding for Computer Systems. Prentice-Hall Upper Saddle River NJ.","DOI":"10.5555\/59854"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_2_1_29_1","volume-title":"SPEC CPU2006 benchmark suite. Retrieved","year":"2011","unstructured":"SPEC2006. 2011. SPEC CPU2006 benchmark suite. Retrieved July 23, 2016 from http:\/\/www.spec.org\/cpu2006\/."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694348"},{"key":"e_1_2_1_31_1","volume-title":"International Conference on High Performance Computing, Networking, Storage and Analysis (SC\u201912)","author":"Sridharan V.","unstructured":"V. Sridharan and D. Liberty. 2012. A field study of DRAM errors. In International Conference on High Performance Computing, Networking, Storage and Analysis (SC\u201912)."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503257"},{"key":"e_1_2_1_33_1","volume-title":"IEEE International Symposium on High Performance Computer Architecture (HPCA\u201915)","author":"Sullivan M.","unstructured":"M. Sullivan, J. Kim, and M. Erez. 2015. Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory. In IEEE International Symposium on High Performance Computer Architecture (HPCA\u201915)."},{"key":"e_1_2_1_34_1","volume-title":"Retrieved","year":"2014","unstructured":"Tezzaron. 2014. Octopus. Retrieved July 23, 2016 from http:\/\/www.tezzaron.com\/."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.5555\/2337159.2337192"},{"key":"e_1_2_1_36_1","volume-title":"12th International Symposium on High-Performance Computer Architecture (HPCA\u201906)","author":"Venkatesan R. K.","unstructured":"R. K. Venkatesan, S. Herr, and E. Rotenberg. 2006. Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM. In 12th International Symposium on High-Performance Computer Architecture (HPCA\u201906). 155--165."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815973"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.103"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2957758","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2957758","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2957758","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:30:01Z","timestamp":1763458201000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2957758"}},"subtitle":["Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory"],"short-title":[],"issued":{"date-parts":[[2016,9,17]]},"references-count":38,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2016,9,17]]}},"alternative-id":["10.1145\/2957758"],"URL":"https:\/\/doi.org\/10.1145\/2957758","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,9,17]]},"assertion":[{"value":"2016-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-06-01","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-09-17","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}