{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,29]],"date-time":"2025-11-29T16:18:23Z","timestamp":1764433103799,"version":"3.45.0"},"reference-count":47,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2018,3,2]],"date-time":"2018-03-02T00:00:00Z","timestamp":1519948800000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1217738"],"award-info":[{"award-number":["1217738"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,4,30]]},"abstract":"<jats:p>\n                    Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high\n                    <jats:italic toggle=\"yes\">I<\/jats:italic>\n                    <jats:sub>ON<\/jats:sub>\n                    <jats:italic toggle=\"yes\">I<\/jats:italic>\n                    <jats:sub>OFF<\/jats:sub>\n                    , and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET\/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET\/BPFET SRAMs exhibit significant advantages in static power, dynamic read\/write noise margin, and read\/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET\/BPFET SRAMs. Our simulations demonstrate that TMDCFET\/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.\n                  <\/jats:p>","DOI":"10.1145\/2967613","type":"journal-article","created":{"date-parts":[[2017,3,6]],"date-time":"2017-03-06T08:56:34Z","timestamp":1488790594000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Monolayer Transistor SRAMs"],"prefix":"10.1145","volume":"13","author":[{"given":"Joydeep","family":"Rakshit","sequence":"first","affiliation":[{"name":"University of Pittsburgh, Benedum Hall, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kartik","family":"Mohanram","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, Benedum Hall, Pittsburgh, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Runlai","family":"Wan","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kai Tak","family":"Lam","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"Guo","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,3,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/513918.514037"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852159"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"e_1_2_1_4_1","unstructured":"ASU. 2012. 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