{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,30]],"date-time":"2025-11-30T08:47:26Z","timestamp":1764492446178,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,7,6]],"date-time":"2016-07-06T00:00:00Z","timestamp":1467763200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,7,6]]},"DOI":"10.1145\/2967878.2967890","type":"proceedings-article","created":{"date-parts":[[2016,9,12]],"date-time":"2016-09-12T13:33:45Z","timestamp":1473687225000},"page":"1-7","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["High Speed, Area and Power Efficient 32-bit Vedic Multipliers"],"prefix":"10.1145","author":[{"given":"Mounika","family":"Mulkalapally","sequence":"first","affiliation":[{"name":"Dept. of Electrical &amp; Computer Engineering, Texas Tech University, Lubbock, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob","family":"Manning","sequence":"additional","affiliation":[{"name":"Dept. of Electrical &amp; Computer Engineering, Texas Tech University, Lubbock, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Gatewood","sequence":"additional","affiliation":[{"name":"Dept. of Electrical &amp; Computer Engineering, Texas Tech University, Lubbock, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tooraj","family":"Nikoubin","sequence":"additional","affiliation":[{"name":"Dept. of Electrical &amp; Computer Engineering, Texas Tech University, Lubbock, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,7,6]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"576","volume-title":"Communications and Informatics (ICACCI), 2015 International Conference","author":"Gokhale G.R","year":"2015","unstructured":"Gokhale G.R , and Bahirgonde , P.D . \" Design of Vedic-multiplier using area-efficient Carry Select Adder\", Advances in Computing , Communications and Informatics (ICACCI), 2015 International Conference , pp. 576 -- 581 , IEEE, August 2015 . Gokhale G.R, and Bahirgonde, P.D. \"Design of Vedic-multiplier using area-efficient Carry Select Adder\", Advances in Computing, Communications and Informatics (ICACCI), 2015 International Conference, pp. 576--581, IEEE, August 2015."},{"key":"e_1_3_2_1_2_1","first-page":"161","volume-title":"IMPACT'09 International","author":"Asati A","year":"2009","unstructured":"Asati A , \"A high-speed, hierarchical 16x 16 array of array multiplier design\", Multimedia, Signal Processing and Communication Technologies , IMPACT'09 International , pp. 161 -- 164 , IEEE, March 2009 . Asati A, \"A high-speed, hierarchical 16x 16 array of array multiplier design\", Multimedia, Signal Processing and Communication Technologies, IMPACT'09 International, pp. 161--164, IEEE, March 2009."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICES.2014.7034180"},{"key":"e_1_3_2_1_4_1","volume-title":"Design of high speed vedic multiplier using vedic mathematics techniques","author":"Kumar G.G.","year":"2012","unstructured":"Kumar G.G. and Charishma V , \" Design of high speed vedic multiplier using vedic mathematics techniques \", International Journal of Scientific and Research Publications , 2(3), p.1. 2012 . Kumar G.G. and Charishma V, \"Design of high speed vedic multiplier using vedic mathematics techniques\", International Journal of Scientific and Research Publications, 2(3), p.1. 2012."},{"issue":"4","key":"e_1_3_2_1_5_1","volume":"3","author":"Aneesh R.","year":"2014","unstructured":"Aneesh R. and Mohan , S.K , \" Design and Analysis of High Speed, Area Optimized 32x32-Bit Multiply Accumlate Unit Based on Vedic Mathematic\" , International Journal of Engineering Research and Technology , 3 ( 4 ), 2014 . Aneesh R. and Mohan, S.K, \"Design and Analysis of High Speed, Area Optimized 32x32-Bit Multiply Accumlate Unit Based on Vedic Mathematic\", International Journal of Engineering Research and Technology, 3(4), 2014.","journal-title":"International Journal of Engineering Research and Technology"},{"key":"e_1_3_2_1_6_1","first-page":"1","volume-title":"Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference","author":"Vijayalakshmi V","year":"2013","unstructured":"Vijayalakshmi V , Seshadri , R. and Ramakrishnan S , \" Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA\", Emerging Trends in VLSI, Embedded System , Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference , pp. 1 -- 5 , IEEE, January 2013 . Vijayalakshmi V, Seshadri, R. and Ramakrishnan S, \"Design and implementation of 32 bit unsigned multiplier using CLAA and CSLA\", Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference, pp. 1--5, IEEE, January 2013."},{"key":"e_1_3_2_1_7_1","first-page":"26","volume-title":"MAC implementation using vedic multiplication algorithm\" International journal of computer applications, 21(7)","author":"Pradhan M","year":"2011","unstructured":"Pradhan M , Panda R. and Sahu S.K. , \" MAC implementation using vedic multiplication algorithm\" International journal of computer applications, 21(7) , pp. 26 -- 28 , 2011 . Pradhan M, Panda R. and Sahu S.K., \"MAC implementation using vedic multiplication algorithm\" International journal of computer applications, 21(7), pp. 26--28, 2011."},{"key":"e_1_3_2_1_8_1","unstructured":"OSU 180nm Standard Cells {online}. Available: http:\/\/vlsiarch.ecen.okstate.edu\/flows\/  OSU 180nm Standard Cells {online}. Available: http:\/\/vlsiarch.ecen.okstate.edu\/flows\/"},{"key":"e_1_3_2_1_9_1","unstructured":"USC 16nm 14nm 7nm 5nm Standard cells. {online}. Available: http:\/\/sportlab.usc.edu\/downloads\/packages\/  USC 16nm 14nm 7nm 5nm Standard cells. {online}. Available: http:\/\/sportlab.usc.edu\/downloads\/packages\/"},{"key":"e_1_3_2_1_10_1","unstructured":"45nm Standard Cell Library. {online}. Available: http:\/\/www.eda.ncsu.edu\/wiki\/FreePDk45:Contents  45nm Standard Cell Library. {online}. Available: http:\/\/www.eda.ncsu.edu\/wiki\/FreePDk45:Contents"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCNT.2015.7395199"}],"event":{"name":"ICCCNT '16: 7th International Conference on Computing Communication and Networking Technologies","sponsor":["University of North Texas University of North Texas"],"location":"Dallas TX USA","acronym":"ICCCNT '16"},"container-title":["Proceedings of the 7th International Conference on Computing Communication and Networking Technologies"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2967878.2967890","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2967878.2967890","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:49:58Z","timestamp":1750218598000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2967878.2967890"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,7,6]]},"references-count":11,"alternative-id":["10.1145\/2967878.2967890","10.1145\/2967878"],"URL":"https:\/\/doi.org\/10.1145\/2967878.2967890","relation":{},"subject":[],"published":{"date-parts":[[2016,7,6]]},"assertion":[{"value":"2016-07-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}