{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:09:40Z","timestamp":1750306180222,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":35,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,9,11]],"date-time":"2016-09-11T00:00:00Z","timestamp":1473552000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,9,11]]},"DOI":"10.1145\/2967938.2967950","type":"proceedings-article","created":{"date-parts":[[2016,8,31]],"date-time":"2016-08-31T12:32:08Z","timestamp":1472646728000},"page":"87-97","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Reduction Drawing"],"prefix":"10.1145","author":[{"given":"Chandan","family":"Reddy","sequence":"first","affiliation":[{"name":"INRIA and \u00c9cole Normale Sup\u00e9rieure, Paris, France"}]},{"given":"Michael","family":"Kruse","sequence":"additional","affiliation":[{"name":"INRIA and \u00c9cole Normale Sup\u00e9rieure, Paris, France"}]},{"given":"Albert","family":"Cohen","sequence":"additional","affiliation":[{"name":"INRIA and \u00c9cole Normale Sup\u00e9rieure, Paris, France"}]}],"member":"320","published-online":{"date-parts":[[2016,9,11]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.17"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1379022.1375595"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1327452.1327492"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1015781018449"},{"key":"e_1_3_2_1_6_1","volume-title":"Polly's polyhedral scheduling in the presence of reductions,\" arXiv preprint arXiv:1505.07716","author":"Doerfert J.","year":"2015","unstructured":"J. Doerfert , K. Streit , S. Hack , and Z. Benaissa , \" Polly's polyhedral scheduling in the presence of reductions,\" arXiv preprint arXiv:1505.07716 , 2015 . J. Doerfert, K. Streit, S. Hack, and Z. Benaissa, \"Polly's polyhedral scheduling in the presence of reductions,\" arXiv preprint arXiv:1505.07716, 2015."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1583991.1584017"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1111037.1111041"},{"key":"e_1_3_2_1_9_1","first-page":"36","volume-title":"ser. Euro-Par","author":"Howes L.","year":"2010","unstructured":"L. Howes , A. Lokhmotov , A. F. Donaldson , and P. H. J. Kelly , \"Towards metaprogramming for parallel systems on a chip,\" in Proceedings of the 2009 International Conference on Parallel Processing , ser. Euro-Par . Berlin, Heidelberg : Springer-Verlag , 2010 , pp. 36 -- 45 . {Online}. Available: http:\/\/dl.acm.org\/citation.cfm?id=1884795.1884803 L. Howes, A. Lokhmotov, A. F. Donaldson, and P. H. J. Kelly, \"Towards metaprogramming for parallel systems on a chip,\" in Proceedings of the 2009 International Conference on Parallel Processing, ser. Euro-Par. Berlin, Heidelberg: Springer-Verlag, 2010, pp. 36--45. {Online}. Available: http:\/\/dl.acm.org\/citation.cfm?id=1884795.1884803"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/109025.109086"},{"key":"e_1_3_2_1_11_1","first-page":"N1124","article-title":"The ANSI C standard (C99)","author":"ISO","year":"1999","unstructured":"ISO , \" The ANSI C standard (C99) ,\" ISO\/IEC, Tech. Rep. WG14 N1124 , 1999 . ISO, \"The ANSI C standard (C99),\" ISO\/IEC, Tech. Rep. WG14 N1124, 1999.","journal-title":"ISO\/IEC, Tech. Rep. WG14"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/20952.20969"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/318789.318810"},{"key":"e_1_3_2_1_14_1","unstructured":"Mark Harris \"Optimizing parallel reduction in CUDA.\" {Online}. Available: https:\/\/docs.nvidia.com\/cuda\/samples\/6_Advanced\/reduction\/doc\/reduction.pdf  Mark Harris \"Optimizing parallel reduction in CUDA.\" {Online}. Available: https:\/\/docs.nvidia.com\/cuda\/samples\/6_Advanced\/reduction\/doc\/reduction.pdf"},{"key":"e_1_3_2_1_15_1","unstructured":"Microsoft \"Parallel patterns library.\" {Online}. Available: https:\/\/msdn.microsoft.com\/en-us\/library\/dd470426.aspx#parallel_reduces  Microsoft \"Parallel patterns library.\" {Online}. Available: https:\/\/msdn.microsoft.com\/en-us\/library\/dd470426.aspx#parallel_reduces"},{"volume-title":"Knoxville","year":"1996","key":"e_1_3_2_1_16_1","unstructured":"MPIF, \"MPI-2 : Extensions to the message-passing interface,\" University of Tennessee , Knoxville , 1996 . MPIF, \"MPI-2: Extensions to the message-passing interface,\" University of Tennessee, Knoxville, 1996."},{"key":"e_1_3_2_1_17_1","first-page":"2167","article-title":"Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM","volume":"1410","author":"Nardi L.","year":"2014","unstructured":"L. Nardi , B. Bodin , M. Z. Zia , J. Mawer , A. Nisbet , P. H. J. Kelly , A. J. Davison , M. Luj\u00e1n , M. F. P. O'Boyle , G. D. Riley , N. Topham , and S. Furber , \" Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM ,\" CoRR , vol. abs\/ 1410 . 2167 , 2014 . {Online}. Available: http:\/\/arxiv.org\/abs\/1410.2167 L. Nardi, B. Bodin, M. Z. Zia, J. Mawer, A. Nisbet, P. H. J. Kelly, A. J. Davison, M. Luj\u00e1n, M. F. P. O'Boyle, G. D. Riley, N. Topham, and S. Furber, \"Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM,\" CoRR, vol. abs\/1410.2167, 2014. {Online}. Available: http:\/\/arxiv.org\/abs\/1410.2167","journal-title":"CoRR"},{"key":"e_1_3_2_1_18_1","unstructured":"Nvidia \"CUB's collective primitives.\" {Online}. Available: https:\/\/nvlabs.github.io\/cub\/  Nvidia \"CUB's collective primitives.\" {Online}. Available: https:\/\/nvlabs.github.io\/cub\/"},{"key":"e_1_3_2_1_19_1","unstructured":"Nvidia \"Thrust C++ library.\" {Online}. Available: https:\/\/developer.nvidia.com\/thrust\/  Nvidia \"Thrust C++ library.\" {Online}. Available: https:\/\/developer.nvidia.com\/thrust\/"},{"key":"e_1_3_2_1_20_1","unstructured":"Nvidia forum \"Faster parallel reductions on Kepler.\" {Online}. Available: https:\/\/devblogs.nvidia.com\/parallelforall\/faster-parallel-reductions-kepler\/  Nvidia forum \"Faster parallel reductions on Kepler.\" {Online}. Available: https:\/\/devblogs.nvidia.com\/parallelforall\/faster-parallel-reductions-kepler\/"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/177492.177494"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224655"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/183432.183525"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.752782"},{"key":"e_1_3_2_1_25_1","first-page":"132","volume-title":"Detection of recurrences in sequential programs with loops,\" in Parallel Architectures and Languages Europe (PARLE)","author":"Redon X.","year":"1993","unstructured":"X. Redon and P. Feautrier , \" Detection of recurrences in sequential programs with loops,\" in Parallel Architectures and Languages Europe (PARLE) . Springer , 1993 , pp. 132 -- 145 . X. Redon and P. Feautrier, \"Detection of recurrences in sequential programs with loops,\" in Parallel Architectures and Languages Europe (PARLE). Springer, 1993, pp. 132--145."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/181181.181319"},{"issue":"3","key":"e_1_3_2_1_27_1","first-page":"4","article-title":"Detection of scans","volume":"15","author":"Redon X.","year":"2000","unstructured":"X. Redon and P. Feautrier , \" Detection of scans ,\" J. of Parallel Algorithms and Applications , vol. 15 , no. 3 -- 4 , pp. 229--263, 2000 . X. Redon and P. Feautrier, \"Detection of scans,\" J. of Parallel Algorithms and Applications, vol. 15, no. 3--4, pp. 229--263, 2000.","journal-title":"J. of Parallel Algorithms and Applications"},{"key":"e_1_3_2_1_28_1","volume-title":"Intel Threading Building Blocks","author":"Reinders J.","year":"2007","unstructured":"J. Reinders , Intel Threading Building Blocks , 1 st ed.\\hskip 1em plus 0.5em minus 0.4em\\relax Sebastopol, CA, USA : O'Reilly & Associates , Inc., 2007 . J. Reinders, Intel Threading Building Blocks, 1st ed.\\hskip 1em plus 0.5em minus 0.4em\\relax Sebastopol, CA, USA: O'Reilly & Associates, Inc., 2007.","edition":"1"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/291889.291893"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2666356.2594342"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/237578.237581"},{"key":"e_1_3_2_1_32_1","unstructured":"The Portland Group \"PGI accelerator compilers with OpenACC directives.\" {Online}. Available: http:\/\/www.pgroup.com\/resources\/accel.htm  The Portland Group \"PGI accelerator compilers with OpenACC directives.\" {Online}. Available: http:\/\/www.pgroup.com\/resources\/accel.htm"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2581122.2544141"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400713"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32820-6_85"},{"key":"e_1_3_2_1_36_1","first-page":"197","volume-title":"Ptype system: A featherweight parallelizability detector,\" in Programming Languages and Systems","author":"Xu D. N.","year":"2004","unstructured":"D. N. Xu , S.-C. Khoo , and Z. Hu , \" Ptype system: A featherweight parallelizability detector,\" in Programming Languages and Systems . Springer , 2004 , pp. 197 -- 212 . D. N. Xu, S.-C. Khoo, and Z. Hu, \"Ptype system: A featherweight parallelizability detector,\" in Programming Languages and Systems. Springer, 2004, pp. 197--212."}],"event":{"name":"PACT '16: International Conference on Parallel Architectures and Compilation","sponsor":["IFIP WG 10.3 IFIP WG 10.3","IEEE TCCA IEEE Computer Society Technical Committee on Computer Architecture","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCPP IEEE Computer Society Technical Committee on Parallel Processing"],"location":"Haifa Israel","acronym":"PACT '16"},"container-title":["Proceedings of the 2016 International Conference on Parallel Architectures and Compilation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2967938.2967950","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2967938.2967950","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:49:59Z","timestamp":1750218599000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2967938.2967950"}},"subtitle":["Language Constructs and Polyhedral Compilation for Reductions on GPU"],"short-title":[],"issued":{"date-parts":[[2016,9,11]]},"references-count":35,"alternative-id":["10.1145\/2967938.2967950","10.1145\/2967938"],"URL":"https:\/\/doi.org\/10.1145\/2967938.2967950","relation":{},"subject":[],"published":{"date-parts":[[2016,9,11]]},"assertion":[{"value":"2016-09-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}