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Superscalar out-of-order processors promise large performance gains, and the memory subsystem is a key part of such a processor that must help supply increased performance. In this article, we describe and explore microarchitectural and circuit-level tradeoffs in the design of such a memory system. We show the significant instructions-per-cycle wins for providing various levels of out-of-order memory access and memory dependence speculation (1.32 \u00d7 SPECint2000) and for the addition of a second-level cache (another 1.60 \u00d7 ). With careful microarchitecture and circuit design, we also achieve a L1 translation lookaside buffers and cache lookup with 29% less logic delay than the simpler Nios II\/f memory system.<\/jats:p>","DOI":"10.1145\/2974022","type":"journal-article","created":{"date-parts":[[2016,12,9]],"date-time":"2016-12-09T17:26:14Z","timestamp":1481304374000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System"],"prefix":"10.1145","volume":"10","author":[{"given":"Henry","family":"Wong","sequence":"first","affiliation":[{"name":"University of Toronto, Toronto, ON, Canada"}]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, ON, Canada"}]},{"given":"Jonathan","family":"Rose","sequence":"additional","affiliation":[{"name":"University of Toronto, Toronto, ON, Canada"}]}],"member":"320","published-online":{"date-parts":[[2016,12,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2010.61"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.69"},{"key":"e_1_2_1_3_1","unstructured":"Altera. 2015. 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