{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T23:15:07Z","timestamp":1763507707241,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,10,24]],"date-time":"2016-10-24T00:00:00Z","timestamp":1477267200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-sa\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003406","name":"Tekes","doi-asserted-by":"publisher","award":["3772\/31\/2014"],"award-info":[{"award-number":["3772\/31\/2014"]}],"id":[{"id":"10.13039\/501100003406","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,10,24]]},"DOI":"10.1145\/2976749.2978420","type":"proceedings-article","created":{"date-parts":[[2016,10,25]],"date-time":"2016-10-25T12:46:35Z","timestamp":1477399595000},"page":"1639-1650","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":24,"title":["\"Make Sure DSA Signing Exponentiations Really are Constant-Time\""],"prefix":"10.1145","author":[{"given":"Cesar","family":"Pereida Garc\u00eda","sequence":"first","affiliation":[{"name":"Aalto University, Espoo, Finland"}]},{"given":"Billy Bob","family":"Brumley","sequence":"additional","affiliation":[{"name":"Tampere University of Technology, Tampere, Finland"}]},{"given":"Yuval","family":"Yarom","sequence":"additional","affiliation":[{"name":"The University of Adelaide & Data61, Adelaide, Australia"}]}],"member":"320","published-online":{"date-parts":[[2016,10,24]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_3_2_1_1_1","DOI":"10.1007\/11967668_15"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1145\/1229285.1266999"},{"key":"e_1_3_2_1_3_1","volume-title":"CHES","author":"Ac\u0131i\u00e7mez Onur","year":"2010","unstructured":"Onur Ac\u0131i\u00e7mez , Billy Bob Brumley, and Philipp Grabher. New results on instruction cache attacks . In CHES , Santa Barbara, CA , US , 2010 . Onur Ac\u0131i\u00e7mez, Billy Bob Brumley, and Philipp Grabher. New results on instruction cache attacks. In CHES, Santa Barbara, CA, US, 2010."},{"key":"e_1_3_2_1_5_1","first-page":"262","volume-title":"ASIACRYPT","author":"Aranha Diego F.","year":"2014","unstructured":"Diego F. Aranha , Pierre-Alain Fouque , Beno\u0131t G\u00e9rard , Jean-Gabriel Kammerer , Mehdi Tibouchi , and Jean-Christophe Zapalowicz . GLV\/ GLS decomposition, power analysis , and attacks on ECDSA signatures with single-bit nonce bias . In ASIACRYPT , pages 262 -- 281 , Kaohsiung, TW , Dec 2014 . Diego F. Aranha, Pierre-Alain Fouque, Beno\u0131t G\u00e9rard, Jean-Gabriel Kammerer, Mehdi Tibouchi, and Jean-Christophe Zapalowicz. GLV\/GLS decomposition, power analysis, and attacks on ECDSA signatures with single-bit nonce bias. In ASIACRYPT, pages 262--281, Kaohsiung, TW, Dec 2014."},{"key":"e_1_3_2_1_6_1","first-page":"19","volume-title":"Linux symposium","author":"Arcangeli Andrea","year":"2009","unstructured":"Andrea Arcangeli , Izik Eidus , and Chris Wright . Increasing memory density by using KSM . In Linux symposium , pages 19 -- 28 , 2009 . Andrea Arcangeli, Izik Eidus, and Chris Wright. Increasing memory density by using KSM. In Linux symposium, pages 19--28, 2009."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1007\/BF02579403"},{"key":"e_1_3_2_1_8_1","volume-title":"Transitions: Recommendation for transitioning the use of cryptographic algorithms and key lengths. NIST Special Publication 800--131A Revision","author":"Barker Elaine","year":"2015","unstructured":"Elaine Barker and Allen Roginsky . Transitions: Recommendation for transitioning the use of cryptographic algorithms and key lengths. NIST Special Publication 800--131A Revision 1, Nov 2015 . URL http:\/\/dx.doi.org\/10.6028\/NIST.SP.800--131Ar1. 10.6028\/NIST.SP.800--131Ar1 Elaine Barker and Allen Roginsky. Transitions: Recommendation for transitioning the use of cryptographic algorithms and key lengths. NIST Special Publication 800--131A Revision 1, Nov 2015. URL http:\/\/dx.doi.org\/10.6028\/NIST.SP.800--131Ar1."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1007\/978-3-662-44709-3_5"},{"key":"e_1_3_2_1_10_1","volume-title":"Cache-timing attacks on AES","author":"Bernstein Daniel J","year":"2005","unstructured":"Daniel J Bernstein . Cache-timing attacks on AES , 2005 . Preprint available at http:\/\/cr.yp.to\/papers.html#cachetiming. Daniel J Bernstein. Cache-timing attacks on AES, 2005. Preprint available at http:\/\/cr.yp.to\/papers.html#cachetiming."},{"key":"e_1_3_2_1_11_1","volume-title":"Nov","author":"Bleichenbacher Daniel","year":"2000","unstructured":"Daniel Bleichenbacher . On the generation of one-time keys in DL signature schemes. Presentation at IEEE P1363 Working Group meeting , Nov 2000 . Daniel Bleichenbacher. On the generation of one-time keys in DL signature schemes. Presentation at IEEE P1363 Working Group meeting, Nov 2000."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.5555\/646761.706148"},{"key":"e_1_3_2_1_13_1","volume-title":"RSA Conference 2006 session DEV-203","author":"Brickell Ernie","year":"2006","unstructured":"Ernie Brickell , Gary Graunke , and Jean-Pierre Seifert . Mitigating cache\/timing based side-channels in AES and RSA software implementations . RSA Conference 2006 session DEV-203 , Feb 2006 . Ernie Brickell, Gary Graunke, and Jean-Pierre Seifert. Mitigating cache\/timing based side-channels in AES and RSA software implementations. RSA Conference 2006 session DEV-203, Feb 2006."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1007\/978-3-642-10366-7_39"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.5555\/2041225.2041252"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1007\/978-3-642-04117-4_31"},{"key":"e_1_3_2_1_17_1","volume-title":"Jan","author":"Intel Corporation","year":"2016","unstructured":"Intel Corporation . Intel 64 and ia-32 architectures optimization reference manual , Jan 2016 . Intel Corporation. Intel 64 and ia-32 architectures optimization reference manual, Jan 2016."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1007\/978-3-642-40349-1_25"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.1109\/SP.2011.22"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1023\/A:1011214926272"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_22_1","DOI":"10.1109\/SP.2015.42"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_23_1","DOI":"10.5555\/1964621.1964651"},{"key":"e_1_3_2_1_24_1","volume-title":"ARMageddon: Last-level cache attacks on mobile devices. arXiv preprint arXiv:1511.04897","author":"Lipp Moritz","year":"2015","unstructured":"Moritz Lipp , Daniel Gruss , Raphael Spreitzer , and Stefan Mangard . ARMageddon: Last-level cache attacks on mobile devices. arXiv preprint arXiv:1511.04897 , 2015 . Moritz Lipp, Daniel Gruss, Raphael Spreitzer, and Stefan Mangard. ARMageddon: Last-level cache attacks on mobile devices. arXiv preprint arXiv:1511.04897, 2015."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_25_1","DOI":"10.1109\/SP.2015.43"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_26_1","DOI":"10.1007\/978-3-642-36095-4_19"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_27_1","DOI":"10.1007\/s00145-002-0021-3"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_28_1","DOI":"10.1023\/A:1025436905711"},{"key":"e_1_3_2_1_29_1","volume-title":"Cache attacks and countermeasures: The case of AES. In ph2006 CT-RSA","author":"Osvik Dag Arne","year":"2006","unstructured":"Dag Arne Osvik , Adi Shamir , and Eran Tromer . Cache attacks and countermeasures: The case of AES. In ph2006 CT-RSA , 2006 . Dag Arne Osvik, Adi Shamir, and Eran Tromer. Cache attacks and countermeasures: The case of AES. In ph2006 CT-RSA, 2006."},{"key":"e_1_3_2_1_30_1","volume-title":"Theoretical use of cache memory as a cryptanalytic side-channel. IACR Cryptology ePrint Archive","author":"Page Dan","year":"2002","unstructured":"Dan Page . Theoretical use of cache memory as a cryptanalytic side-channel. IACR Cryptology ePrint Archive , 2002 : 169, 2002. Dan Page. Theoretical use of cache memory as a cryptanalytic side-channel. IACR Cryptology ePrint Archive, 2002: 169, 2002."},{"key":"e_1_3_2_1_31_1","volume-title":"BSDCan 2005","author":"Percival Colin","year":"2005","unstructured":"Colin Percival . Cache missing for fun and profit . In BSDCan 2005 , Ottawa, CA , 2005 . Colin Percival. Cache missing for fun and profit. In BSDCan 2005, Ottawa, CA, 2005."},{"key":"e_1_3_2_1_32_1","volume-title":"USA","author":"de Pol Van","year":"2015","unstructured":"Van de Pol , Nigel P. Smart , and Yuval Yarom . Just a little bit more. In ph2015 CT-RSA, pages 3--21, San Francisco, CA , USA , Apr 2015 . Van de Pol, Nigel P. Smart, and Yuval Yarom. Just a little bit more. In ph2015 CT-RSA, pages 3--21, San Francisco, CA, USA, Apr 2015."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_33_1","DOI":"10.1109\/PROC.1975.9939"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_34_1","DOI":"10.1007\/BF01581144"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_35_1","DOI":"10.5555\/225160.225208"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_36_1","DOI":"10.5555\/1060289.1060307"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_37_1","DOI":"10.1007\/978-3-540-24654-1_4"},{"key":"e_1_3_2_1_38_1","volume-title":"March","author":"Wuille Pieter","year":"2014","unstructured":"Pieter Wuille . Dealling with malleability. https:\/\/github.com\/bitcoin\/bips\/blob\/master\/bip-0062.mediawiki , March 2014 . Pieter Wuille. Dealling with malleability. https:\/\/github.com\/bitcoin\/bips\/blob\/master\/bip-0062.mediawiki, March 2014."},{"key":"e_1_3_2_1_40_1","first-page":"719","volume-title":"23rd USENIX Security","author":"Yarom Yuval","year":"2014","unstructured":"Yuval Yarom and Katrina Falkner . Flush+Reload : a high resolution, low noise, L3 cache side-channel attack . In 23rd USENIX Security , pages 719 -- 732 , San Diego, CA, US , 2014 . Yuval Yarom and Katrina Falkner. Flush+Reload: a high resolution, low noise, L3 cache side-channel attack. In 23rd USENIX Security, pages 719--732, San Diego, CA, US, 2014."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_41_1","DOI":"10.1007\/978-3-662-53140-2_17"}],"event":{"sponsor":["SIGSAC ACM Special Interest Group on Security, Audit, and Control"],"acronym":"CCS'16","name":"CCS'16: 2016 ACM SIGSAC Conference on Computer and Communications Security","location":"Vienna Austria"},"container-title":["Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2976749.2978420","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2976749.2978420","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:49:54Z","timestamp":1750218594000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2976749.2978420"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10,24]]},"references-count":38,"alternative-id":["10.1145\/2976749.2978420","10.1145\/2976749"],"URL":"https:\/\/doi.org\/10.1145\/2976749.2978420","relation":{},"subject":[],"published":{"date-parts":[[2016,10,24]]},"assertion":[{"value":"2016-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}