{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:09:29Z","timestamp":1750306169998,"version":"3.41.0"},"reference-count":21,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T00:00:00Z","timestamp":1480550400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"ERC senior","award":["NanoSys ERC-2009-AdG-246810"],"award-info":[{"award-number":["NanoSys ERC-2009-AdG-246810"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,4,30]]},"abstract":"<jats:p>This article first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and we report the results of a SPICE-based analysis of the effects of faults on the behavior of some basic gates implemented with them. Hence, we show that the considered devices are able to intrinsically tolerate a rather high number of faults. We finally exploit this property to build a robust and scalable adder whose area, performance, and leakage power characteristics are improved by 15%, 18%, and 12%;, respectively, when compared to an equivalent FinFET solution at 22nm technology node.<\/jats:p>","DOI":"10.1145\/2988234","type":"journal-article","created":{"date-parts":[[2016,12,1]],"date-time":"2016-12-01T19:13:10Z","timestamp":1480619590000},"page":"1-13","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors"],"prefix":"10.1145","volume":"13","author":[{"given":"Hassan Ghasemzadeh","family":"Mohammadi","sequence":"first","affiliation":[{"name":"Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"University of Utah, UT, USA"}]},{"given":"Jian","family":"Zhang","sequence":"additional","affiliation":[{"name":"Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"Giovanni De","family":"Micheli","sequence":"additional","affiliation":[{"name":"Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Switzerland"}]},{"given":"Ernesto","family":"Sanchez","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]},{"given":"Matteo Sonza","family":"Reorda","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Torino, Italy"}]}],"member":"320","published-online":{"date-parts":[[2016,12]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/1768409.1768469"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346842"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2010.5603933"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2085250"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2066530"},{"key":"e_1_2_1_6_1","unstructured":"M. L. Bushnell and V. D. Agrawal. 2000. Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Springer Science+Business Media New York.  M. L. Bushnell and V. D. Agrawal. 2000. Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits. Springer Science+Business Media New York."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479004"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2329919"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485442"},{"volume-title":"Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201915)","author":"Ghasemzadeh Mohammadi H.","key":"e_1_2_1_10_1","unstructured":"H. Ghasemzadeh Mohammadi , P.-E. Gaillardon , and G. De Micheli . 2015. Fault modeling in controllable polarity silicon nanowire circuits . In Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201915) . 453--458. H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli. 2015. Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings of Design, Automation 8 Test in Europe Conference 8 Exhibition (DATE\u201915). 453--458."},{"key":"e_1_2_1_11_1","volume-title":"From defect analysis to gate-level fault modeling of controllable-polarity silicon nanowires","author":"Ghasemzadeh Mohammadi H.","year":"2015","unstructured":"H. Ghasemzadeh Mohammadi , P.-E. Gaillardon , and G. De Micheli . 2015. From defect analysis to gate-level fault modeling of controllable-polarity silicon nanowires . IEEE Transactions on Nanotechnology . 2015 . H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli. 2015. From defect analysis to gate-level fault modeling of controllable-polarity silicon nanowires. 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