{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:10:11Z","timestamp":1750306211533,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":62,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,10,3]],"date-time":"2016-10-03T00:00:00Z","timestamp":1475452800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,10,3]]},"DOI":"10.1145\/2989081.2989106","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T15:58:54Z","timestamp":1476979134000},"page":"164-176","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Twin-Load"],"prefix":"10.1145","author":[{"given":"Zehan","family":"Cui","sequence":"first","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS"}]},{"given":"Tianyue","family":"Lu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS and University of Chinese Academy of Sciences"}]},{"given":"Sally A.","family":"McKee","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology"}]},{"given":"Mingyu","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS"}]},{"given":"Haiyang","family":"Pan","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS and University of Chinese Academy of Sciences"}]},{"given":"Yuan","family":"Ruan","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS"}]}],"member":"320","published-online":{"date-parts":[[2016,10,3]]},"reference":[{"unstructured":"JEDEC\n  : Global standards for the microelectronics industry. http:\/\/www.jedec.org.  JEDEC: Global standards for the microelectronics industry. http:\/\/www.jedec.org.","key":"e_1_3_2_1_1_1"},{"unstructured":"The LLVM compiler infrastructure. http:\/\/llvm.org\/.  The LLVM compiler infrastructure. http:\/\/llvm.org\/.","key":"e_1_3_2_1_2_1"},{"unstructured":"Memcached --- a distributed memory object caching system. http:\/\/memcached.org\/.  Memcached --- a distributed memory object caching system. http:\/\/memcached.org\/.","key":"e_1_3_2_1_3_1"},{"unstructured":"NAS Parallel Benchmarks. http:\/\/www.nas.nasa.gov\/publications\/npb.html.  NAS Parallel Benchmarks. http:\/\/www.nas.nasa.gov\/publications\/npb.html.","key":"e_1_3_2_1_4_1"},{"unstructured":"NU-Minebench. http:\/\/cucis.ece.northwestern.edu\/projects\/DMS\/MineBench.html.  NU-Minebench. http:\/\/cucis.ece.northwestern.edu\/projects\/DMS\/MineBench.html.","key":"e_1_3_2_1_5_1"},{"unstructured":"The PARSEC Benchmark Suite. http:\/\/parsec.cs.princeton.edu\/parsec3-doc.htm.  The PARSEC Benchmark Suite. http:\/\/parsec.cs.princeton.edu\/parsec3-doc.htm.","key":"e_1_3_2_1_6_1"},{"unstructured":"The Graph500 List. http:\/\/www.graph500.org\/.  The Graph500 List. http:\/\/www.graph500.org\/.","key":"e_1_3_2_1_7_1"},{"unstructured":"Advanced Micro Devices Inc. Family 16h models 00h - 0fh amd opteron\u00aeprocessor product data sheet. Publication 53102 http:\/\/support.amd.com\/TechDocs\/53102_Opteron_Product_Data_Sheet.pdf Feb. 2014.  Advanced Micro Devices Inc. Family 16h models 00h - 0fh amd opteron\u00aeprocessor product data sheet. Publication 53102 http:\/\/support.amd.com\/TechDocs\/53102_Opteron_Product_Data_Sheet.pdf Feb. 2014.","key":"e_1_3_2_1_8_1"},{"unstructured":"AgigA Technology Inc. AGIGARAM DDR3 NVDIMM. http:\/\/www.agigatech.com\/ddr3.php.  AgigA Technology Inc. AGIGARAM DDR3 NVDIMM. http:\/\/www.agigatech.com\/ddr3.php.","key":"e_1_3_2_1_9_1"},{"key":"e_1_3_2_1_10_1","first-page":"43761D","article-title":"ACP --- the truth about power consumption starts here","author":"Inc AMD","year":"2010","unstructured":"AMD , Inc . ACP --- the truth about power consumption starts here . AMD White Paper PID 43761D , 2010 . AMD, Inc. ACP --- the truth about power consumption starts here. AMD White Paper PID 43761D, 2010.","journal-title":"AMD White Paper PID"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01741-4","volume-title":"The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines","author":"Barroso L.","year":"2013","unstructured":"L. Barroso , J. Clidaras , and U. H\u00f6lzle . The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines , 2 nd Ed. Morgan & Claypool Synthesis Lectures on Computer Architecture , July 2013 . L. Barroso, J. Clidaras, and U. H\u00f6lzle. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, 2nd Ed. Morgan & Claypool Synthesis Lectures on Computer Architecture, July 2013.","edition":"2"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1016\/S0169-7552(98)00110-X"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1007\/s11390-014-1428-7"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.5555\/2337159.2337204"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_15_1","DOI":"10.1145\/1629911.1630086"},{"unstructured":"Diablo Technology Inc. Memory channel storage. http:\/\/www.diablo-technologies.com\/memory-channel-storage\/.  Diablo Technology Inc. Memory channel storage. http:\/\/www.diablo-technologies.com\/memory-channel-storage\/.","key":"e_1_3_2_1_16_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1109\/ISCA.2005.6"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1109\/PACT.2011.71"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_19_1","DOI":"10.1109\/HPCA.2013.6522338"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_20_1","DOI":"10.1145\/1687399.1687491"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1145\/2628071.2628089"},{"key":"e_1_3_2_1_22_1","volume-title":"Hybrid Memory Cube Specification 1.0","author":"Hybrid Memory Cube Consortium","year":"2013","unstructured":"Hybrid Memory Cube Consortium . Hybrid Memory Cube Specification 1.0 , 2013 . Hybrid Memory Cube Consortium. Hybrid Memory Cube Specification 1.0, 2013."},{"key":"e_1_3_2_1_23_1","volume-title":"Feb.","author":"Intel Corp. Intel\u00aec102\/c104 scalable memory buffer datasheet.","year":"2014","unstructured":"Intel Corp. Intel\u00aec102\/c104 scalable memory buffer datasheet. Datasheet Reference Number:330032-001 , Feb. 2014 . Intel Corp. Intel\u00aec102\/c104 scalable memory buffer datasheet. Datasheet Reference Number:330032-001, Feb. 2014."},{"key":"e_1_3_2_1_24_1","volume-title":"Intel\u00aeXeon\u00aeprocessor E7 v2 2800\/4800\/8800 product family. Datasheet Reference Numbers: 329594-001, 329595-002","author":"Intel Corp.","year":"2014","unstructured":"Intel Corp. Intel\u00aeXeon\u00aeprocessor E7 v2 2800\/4800\/8800 product family. Datasheet Reference Numbers: 329594-001, 329595-002 , 329595-003, Mar. 2014 . Intel Corp. Intel\u00aeXeon\u00aeprocessor E7 v2 2800\/4800\/8800 product family. Datasheet Reference Numbers: 329594-001, 329595-002, 329595-003, Mar. 2014."},{"key":"e_1_3_2_1_25_1","volume-title":"Datasheet: Intel Xeon processor E5 v2 1600\/2600\/4600 product family","author":"Intel Corporation","year":"2014","unstructured":"Intel Corporation . Datasheet: Intel Xeon processor E5 v2 1600\/2600\/4600 product family , 2014 . Intel Corporation. Datasheet: Intel Xeon processor E5 v2 1600\/2600\/4600 product family, 2014."},{"key":"e_1_3_2_1_26_1","volume-title":"ITRS report 2012 update","author":"ITRS.","year":"2012","unstructured":"ITRS. ITRS report 2012 update , 2012 . ITRS. ITRS report 2012 update, 2012."},{"key":"e_1_3_2_1_27_1","volume-title":"FBDIMM standard: DDR2 SDRAM fully buffered DIMM (FBDIMM) design standard","author":"JEDEC.","year":"2007","unstructured":"JEDEC. FBDIMM standard: DDR2 SDRAM fully buffered DIMM (FBDIMM) design standard , 2007 . JEDEC. FBDIMM standard: DDR2 SDRAM fully buffered DIMM (FBDIMM) design standard, 2007."},{"key":"e_1_3_2_1_28_1","volume-title":"DDR3 SDRAM specification","author":"JEDEC.","year":"2010","unstructured":"JEDEC. DDR3 SDRAM specification , 2010 . JEDEC. DDR3 SDRAM specification, 2010."},{"unstructured":"JEDEC. 288-pin 1.2 V (VDD) PC4-1600\/PC4-1866\/PC4-2133\/PC4-2400\/PC4-2666\/PC4-3200 DDR4 SDRAM load reduced DIMM design specification 2015.  JEDEC. 288-pin 1.2 V (VDD) PC4-1600\/PC4-1866\/PC4-2133\/PC4-2400\/PC4-2666\/PC4-3200 DDR4 SDRAM load reduced DIMM design specification 2015.","key":"e_1_3_2_1_29_1"},{"unstructured":"JEDEC. 288-pin 1.2 V (VDD) PC4-1600\/PC4-1866\/PC4-2133\/PC4-2400\/PC4-2666\/PC4-3200 DDR4 SDRAM registered DIMM design specification 2015.  JEDEC. 288-pin 1.2 V (VDD) PC4-1600\/PC4-1866\/PC4-2133\/PC4-2400\/PC4-2666\/PC4-3200 DDR4 SDRAM registered DIMM design specification 2015.","key":"e_1_3_2_1_30_1"},{"key":"e_1_3_2_1_31_1","volume-title":"Jedec announces support for nvdimm hybrid memory modules. https:\/\/www.jedec.org\/news\/pressreleases\/jedec-announces-support-nvdimm-hybrid-memory-modules","author":"JEDEC.","year":"2015","unstructured":"JEDEC. Jedec announces support for nvdimm hybrid memory modules. https:\/\/www.jedec.org\/news\/pressreleases\/jedec-announces-support-nvdimm-hybrid-memory-modules , 2015 . JEDEC. Jedec announces support for nvdimm hybrid memory modules. https:\/\/www.jedec.org\/news\/pressreleases\/jedec-announces-support-nvdimm-hybrid-memory-modules, 2015."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_32_1","DOI":"10.1145\/1555754.1555758"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_33_1","DOI":"10.1109\/ICCD.2011.6081427"},{"unstructured":"Lenovo Group Ltd. Lenovo eXFlash DDR3 Storage DIMMs. https:\/\/lenovopress.com\/tips1141-exflash-dimms.  Lenovo Group Ltd. Lenovo eXFlash DDR3 Storage DIMMs. https:\/\/lenovopress.com\/tips1141-exflash-dimms.","key":"e_1_3_2_1_34_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_35_1","DOI":"10.1109\/MM.2012.25"},{"key":"e_1_3_2_1_36_1","first-page":"28","article-title":"Best practices for oversubscription of CPU, memory and storage in vSphere virtual environments","volume":"2013","author":"Lowe S.","year":"2013","unstructured":"S. Lowe . Best practices for oversubscription of CPU, memory and storage in vSphere virtual environments . Dell Whitepaper-vSphere-Environ-US-KS- 2013-03 - 28 , 2013 . S. Lowe. Best practices for oversubscription of CPU, memory and storage in vSphere virtual environments. Dell Whitepaper-vSphere-Environ-US-KS-2013-03-28, 2013.","journal-title":"Dell Whitepaper-vSphere-Environ-US-KS-"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_37_1","DOI":"10.1145\/1065010.1065034"},{"unstructured":"Micron Technology Inc. NVDIMM. https:\/\/www.micron.com\/products\/dram-modules\/nvdimm#\/.  Micron Technology Inc. NVDIMM. https:\/\/www.micron.com\/products\/dram-modules\/nvdimm#\/.","key":"e_1_3_2_1_38_1"},{"unstructured":"Micron Technology Inc. TN-41-01: Calculating memory system power for DDR3 2007.  Micron Technology Inc. TN-41-01: Calculating memory system power for DDR3 2007.","key":"e_1_3_2_1_39_1"},{"key":"e_1_3_2_1_40_1","series-title":"Analog Circuits and Signal Processing","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1007\/978-1-4614-8881-1_9","volume-title":"Embedded Memory Design for Multi-Core and Systems on Chip","author":"Mohammad B.","year":"2014","unstructured":"B. Mohammad . Emerging memory technology opportunities and challenges . In Embedded Memory Design for Multi-Core and Systems on Chip , volume 116 of Analog Circuits and Signal Processing , pages 83 -- 89 . Springer New York , 2014 . B. Mohammad. Emerging memory technology opportunities and challenges. In Embedded Memory Design for Multi-Core and Systems on Chip, volume 116 of Analog Circuits and Signal Processing, pages 83--89. Springer New York, 2014."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_41_1","DOI":"10.1145\/2485922.2485929"},{"unstructured":"Netlist Inc. NVvaultTM DDR4 (NV4). http:\/\/www.netlist.com\/products\/vault-memory-storage\/nvvault-ddr4-nvdimm\/default.aspx.  Netlist Inc. NVvaultTM DDR4 (NV4). http:\/\/www.netlist.com\/products\/vault-memory-storage\/nvvault-ddr4-nvdimm\/default.aspx.","key":"e_1_3_2_1_42_1"},{"unstructured":"Oracle Inc. Oracle's SPARC T7 and SPARC M7 server architecture. White Paper 2702877 http:\/\/www.oracle.com\/technetwork\/server-storage\/sun-sparc-enterprise\/documentation\/sparc-t7-m7-server-architecture-2702877.pdf 2016.  Oracle Inc. Oracle's SPARC T7 and SPARC M7 server architecture. White Paper 2702877 http:\/\/www.oracle.com\/technetwork\/server-storage\/sun-sparc-enterprise\/documentation\/sparc-t7-m7-server-architecture-2702877.pdf 2016.","key":"e_1_3_2_1_43_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_44_1","DOI":"10.1145\/2540708.2540724"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_45_1","DOI":"10.1109\/HPCA.2010.5416645"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_46_1","DOI":"10.1145\/1555754.1555760"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_47_1","DOI":"10.1145\/1995896.1995911"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_48_1","DOI":"10.1109\/L-CA.2011.4"},{"unstructured":"Sandisk Corp. ULLtraDIMM SSDs. http:\/\/web.sandisk.com\/enterprise\/ulltradimm-ssd\/.  Sandisk Corp. ULLtraDIMM SSDs. http:\/\/web.sandisk.com\/enterprise\/ulltradimm-ssd\/.","key":"e_1_3_2_1_49_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_50_1","DOI":"10.1145\/2641229"},{"unstructured":"A. Shimpi. AMD: still in the game: The AMD memory roadmap: Ddr3 fbd and g3mx examined. AnandTech http:\/\/www.anandtech.com\/show\/2287\/4 July 2007.  A. Shimpi. AMD: still in the game: The AMD memory roadmap: Ddr3 fbd and g3mx examined. AnandTech http:\/\/www.anandtech.com\/show\/2287\/4 July 2007.","key":"e_1_3_2_1_51_1"},{"unstructured":"SMIC. Advanced Logic - 40nm 65\/55nnm. http:\/\/www.smics.com\/eng\/foundry\/technology\/advanced_logic.php.  SMIC. Advanced Logic - 40nm 65\/55nnm. http:\/\/www.smics.com\/eng\/foundry\/technology\/advanced_logic.php.","key":"e_1_3_2_1_52_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_53_1","DOI":"10.1147\/JRD.2014.2376131"},{"unstructured":"Synopsys Inc. Design compiler 2010. http:\/\/www.synopsys.com\/Tools\/Implementation\/RTLSynthesis\/DesignCompiler\/Pages\/default.aspx.  Synopsys Inc. Design compiler 2010. http:\/\/www.synopsys.com\/Tools\/Implementation\/RTLSynthesis\/DesignCompiler\/Pages\/default.aspx.","key":"e_1_3_2_1_54_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_55_1","DOI":"10.1147\/rd.452.0271"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_56_1","DOI":"10.1145\/2000064.2000115"},{"key":"e_1_3_2_1_57_1","volume-title":"Hot Chips","author":"Oracle's B.","year":"2015","unstructured":"B. V. and R. P. Oracle's Sonoma processor : Advanced low-cost SPARC processor for enterprise workloads . In Hot Chips , Aug. 2015 . B. V. and R. P. Oracle's Sonoma processor: Advanced low-cost SPARC processor for enterprise workloads. In Hot Chips, Aug. 2015."},{"unstructured":"Viking Technology. ArxCis-NV: Non-Volatile Memory Technology. http:\/\/www.vikingtechnology.com\/arxcis-nv.  Viking Technology. ArxCis-NV: Non-Volatile Memory Technology. http:\/\/www.vikingtechnology.com\/arxcis-nv.","key":"e_1_3_2_1_58_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_59_1","DOI":"10.1109\/JPROC.2010.2070050"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_60_1","DOI":"10.1109\/ICCD.2012.6378661"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_61_1","DOI":"10.1145\/2808233"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_62_1","DOI":"10.1145\/1555754.1555759"}],"event":{"acronym":"MEMSYS '16","name":"MEMSYS '16: The Second International Symposium on Memory Systems","location":"Alexandria VA USA"},"container-title":["Proceedings of the Second International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2989081.2989106","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2989081.2989106","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:50:41Z","timestamp":1750218641000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2989081.2989106"}},"subtitle":["Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems"],"short-title":[],"issued":{"date-parts":[[2016,10,3]]},"references-count":62,"alternative-id":["10.1145\/2989081.2989106","10.1145\/2989081"],"URL":"https:\/\/doi.org\/10.1145\/2989081.2989106","relation":{},"subject":[],"published":{"date-parts":[[2016,10,3]]},"assertion":[{"value":"2016-10-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}