{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:54:40Z","timestamp":1750308880462,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,4,14]],"date-time":"2017-04-14T00:00:00Z","timestamp":1492128000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Focus Center Research Program"},{"name":"SRC program"},{"name":"two of the six SRC STARnet Centers"},{"name":"Systems on Nanoscale Information fabriCs (SONIC) and Center for Future Architectures Research"},{"name":"Gigascale Systems Research Center"},{"name":"MARCO and DARPA"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"<jats:p>With increasing technology scaling and design complexity there are increasing threats from device and circuit failures. This is expected to worsen with post-CMOS devices. Current error-resilient solutions ensure reliability of circuits through protection mechanisms such as redundancy, error correction, and recovery. However, the costs of these solutions may be high, rendering them impractical. In contrast, error-tolerant solutions allow errors in the computation and are positioned to be suitable for error-tolerant applications such as media applications. For such programmable error-tolerant processors, the Instruction-Set-Architecture (ISA) no longer serves as a specification since it is acceptable for the processor to allow for errors during the execution of instructions. In this work, we address this specification gap by defining the basic requirements needed for an error-tolerant processor to provide acceptable results. Furthermore, we formally define properties that capture these requirements. Based on this, we propose the Partially Protected Uniprocessor (PPU), an error-tolerant processor that aims to meet these requirements with low-cost microarchitectural support. These protection mechanisms convert potentially fatal control errors to potentially tolerable data errors instead of ensuring instruction-level or byte-level correctness. The protection mechanisms in PPU protect the system against crashes, unresponsiveness, and external device corruption. In addition, they also provide support for achieving acceptable result quality. Additionally, we provide a methodology that formally proves the specification properties on PPU using model checking. This methodology uses models for the hardware and software that are integrated with the fault and recovery models. Finally, we experimentally demonstrate the results of model checking and the application-level quality of results for PPU.<\/jats:p>","DOI":"10.1145\/2990502","type":"journal-article","created":{"date-parts":[[2017,4,14]],"date-time":"2017-04-14T12:18:48Z","timestamp":1492172328000},"page":"1-29","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["PPU"],"prefix":"10.1145","volume":"13","author":[{"given":"Pareesa Ameneh","family":"Golnari","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ, US"}]},{"given":"Yavuz","family":"Yetim","sequence":"additional","affiliation":[{"name":"Princeton University"}]},{"given":"Margaret","family":"Martonosi","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, US"}]},{"given":"Yakir","family":"Vizel","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, US"}]},{"given":"Sharad","family":"Malik","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, US"}]}],"member":"320","published-online":{"date-parts":[[2017,4,14]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000118"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Andrew W. Appel. 1998. Modern Compiler Implementation in ML. Cambridge University Press.  Andrew W. Appel. 1998. Modern Compiler Implementation in ML. Cambridge University Press.","DOI":"10.1017\/CBO9780511811449"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1999.809458"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1809028.1806620"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2544173.2509546"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2179038"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s100090050046"},{"key":"e_1_2_1_9_1","unstructured":"Edmund Clarke Clarke Orna Grumberg and Doron Peled. 1999. Model Checking. MIT Press.  Edmund Clarke Clarke Orna Grumberg and Doron Peled. 1999. Model Checking. MIT Press."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/363095.363139"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/321296.321310"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151008"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.48"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372582"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2384616.2384619"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313834"},{"key":"e_1_2_1_18_1","unstructured":"ITRS. 2011. ITRS Process Integration Devices and Structures. Retrieved from http:\/\/www.itrs.net\/Links\/2005ITRS\/Home2005.htm  ITRS. 2011. ITRS Process Integration Devices and Structures. Retrieved from http:\/\/www.itrs.net\/Links\/2005ITRS\/Home2005.htm"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.253"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2121913"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.1950391"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.18"},{"volume":"49","volume-title":"ACM SIGPLAN Notices","author":"Misailovic Sasa","key":"e_1_2_1_25_1"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"e_1_2_1_27_1","unstructured":"Shubu Mukherjee. 2011. Architecture Design for Soft Errors. Morgan Kaufmann.  Shubu Mukherjee. 2011. Architecture Design for Soft Errors. Morgan Kaufmann."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457181"},{"key":"e_1_2_1_29_1","unstructured":"David A. Patterson and John L. Hennessy. 2012. Computer Organization and Design: The Hardware\/Software Interface. Academic Press.  David A. Patterson and John L. Hennessy. 2012. Computer Organization and Design: The Hardware\/Software Interface. Academic Press."},{"volume-title":"Proceedings of the USENIX Annual Technical Conference, General Track. 105--120","author":"Prabhakaran Vijayan","key":"e_1_2_1_30_1"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993518"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2025113.2025133"},{"volume-title":"Proceedings of the 15th Workshop on Hot Topics in Operating Systems (HotOS XV).","year":"2015","author":"Stanley-Marbell Phillip","key":"e_1_2_1_33_1"},{"volume-title":"Image Fusion: Algorithms and Applications","year":"2008","author":"Stathaki Tania","key":"e_1_2_1_34_1"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45937-5_14"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"},{"key":"e_1_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Qiang Xu Todd Mytkowicz and Nam Sung Kim. 2016. Approximate computing: A survey. IEEE Design 8 Test 33 1 (2016) 8--22.  Qiang Xu Todd Mytkowicz and Nam Sung Kim. 2016. Approximate computing: A survey. IEEE Design 8 Test 33 1 (2016) 8--22.","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1189256.1189259"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694354"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.055"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2990502","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2990502","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2990502","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T21:15:24Z","timestamp":1750281324000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2990502"}},"subtitle":["A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees"],"short-title":[],"issued":{"date-parts":[[2017,4,14]]},"references-count":40,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,7,31]]}},"alternative-id":["10.1145\/2990502"],"URL":"https:\/\/doi.org\/10.1145\/2990502","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2017,4,14]]},"assertion":[{"value":"2015-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-04-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}