{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,20]],"date-time":"2025-12-20T22:03:43Z","timestamp":1766268223650,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T00:00:00Z","timestamp":1489708800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"MOE Tier-2","award":["MOE2015-T2-2-013"],"award-info":[{"award-number":["MOE2015-T2-2-013"]}]},{"name":"Singapore NRF-CRP","award":["NRF-CRP9-2011-01"],"award-info":[{"award-number":["NRF-CRP9-2011-01"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"<jats:p>The recently emerging resistive random-access memory (RRAM) can provide nonvolatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for the low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM crossbar--based computing is mainly assumed as a multilevel analog computing, whose result is sensitive to process nonuniformity as well as additional overhead from AD-conversion and I\/O. In this article, we explore the matrix-vector multiplication accelerator on a binary RRAM crossbar with adaptive 1-bit-comparator--based parallel conversion. Moreover, a distributed in-memory computing architecture is also developed with the according control protocol. Both memory array and logic accelerator are implemented on the binary RRAM crossbar, where the logic-memory pair can be distributed with the control bus protocol. Experimental results have shown that compared to the analog RRAM crossbar, the proposed binary RRAM crossbar can achieve significant area savings with better calculation accuracy. Moreover, significant speedup can be achieved for matrix-vector multiplication in neural network--based machine learning such that the overall training and testing time can be both reduced. In addition, large energy savings can be also achieved when compared to the traditional CMOS-based out-of-memory computing architecture.<\/jats:p>","DOI":"10.1145\/2996192","type":"journal-article","created":{"date-parts":[[2017,3,20]],"date-time":"2017-03-20T12:29:43Z","timestamp":1490012983000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":39,"title":["Distributed In-Memory Computing on Binary RRAM Crossbar"],"prefix":"10.1145","volume":"13","author":[{"given":"Leibin","family":"Ni","sequence":"first","affiliation":[{"name":"Nanyang Technological University, VIRTUS, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hantao","family":"Huang","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, VIRTUS, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zichuan","family":"Liu","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, VIRTUS, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rajiv V.","family":"Joshi","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao","family":"Yu","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, VIRTUS, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,3,17]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070830"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/2755753.2755947"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"e_1_2_1_4_1","volume-title":"Proceedings of the International Conference on Artificial Intelligence and Statistics. 215--223","author":"Coates Adam","year":"2011","unstructured":"Adam Coates , Andrew Y. Ng , and Honglak Lee . 2011 . An analysis of single-layer networks in unsupervised feature learning . In Proceedings of the International Conference on Artificial Intelligence and Statistics. 215--223 . Adam Coates, Andrew Y. Ng, and Honglak Lee. 2011. An analysis of single-layer networks in unsupervised feature learning. In Proceedings of the International Conference on Artificial Intelligence and Statistics. 215--223."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2312177"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2136443"},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the International Conference on Artificial Intelligence and Statistics. 249--256","author":"Glorot Xavier","year":"2010","unstructured":"Xavier Glorot and Yoshua Bengio . 2010 . Understanding the difficulty of training deep feedforward neural networks . In Proceedings of the International Conference on Artificial Intelligence and Statistics. 249--256 . Xavier Glorot and Yoshua Bengio. 2010. Understanding the difficulty of training deep feedforward neural networks. In Proceedings of the International Conference on Artificial Intelligence and Statistics. 249--256."},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915)","author":"Gu Peng","year":"2015","unstructured":"Peng Gu , Boxun Li , Tianqi Tang , Shimeng Yu , Yu Cao , Yu Wang , and Huazhong Yang . 2015 . Technological exploration of RRAM crossbar array for matrix-vector multiplication . In Proceedings of the 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915) . IEEE, Los Alamitos, CA, 106--111. Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, and Huazhong Yang. 2015. Technological exploration of RRAM crossbar array for matrix-vector multiplication. In Proceedings of the 2015 20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915). IEEE, Los Alamitos, CA, 106--111."},{"volume-title":"Neural Networks and Learning Machines","author":"Haykin Simon S.","key":"e_1_2_1_9_1","unstructured":"Simon S. Haykin . 2009. Neural Networks and Learning Machines . Vol. 3 . Pearson Education, Upper Saddle River, NJ. Simon S. Haykin. 2009. Neural Networks and Learning Machines. Vol. 3. Pearson Education, Upper Saddle River, NJ."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1002\/wics.18"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2006.18.7.1527"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2005.12.126"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/2132325.2132381"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2014.7021234"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl203687n"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2012.6398336"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2009.26"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2014.2326798"},{"volume-title":"Neural Networks: Tricks of the Trade","author":"LeCun Yann A.","key":"e_1_2_1_20_1","unstructured":"Yann A. LeCun , L\u00e9on Bottou , Genevieve B. Orr , and Klaus-Robert M\u00fcller . 2012. Efficient backprop . In Neural Networks: Tricks of the Trade . Springer , 9--48. Yann A. LeCun, L\u00e9on Bottou, Genevieve B. Orr, and Klaus-Robert M\u00fcller. 2012. Efficient backprop. In Neural Networks: Tricks of the Trade. Springer, 9--48."},{"volume-title":"Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201908)","author":"Lee H. Y.","key":"e_1_2_1_21_1","unstructured":"H. Y. Lee , P. S. Che , T. Y. Wu , Y. S. Che , C. C. Wan , P. J. Tzen , C. H. Lin , F. Chen , C. H. Lien , and M. J. Tsai . 2008. Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM . In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201908) . IEEE, Los Alamitos, CA, 1--4. H. Y. Lee, P. S. Che, T. Y. Wu, Y. S. Che, C. C. Wan, P. J. Tzen, C. H. Lin, F. Chen, C. H. Lien, and M. J. Tsai. 2008. Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM. In Proceedings of the IEEE International Electron Devices Meeting (IEDM\u201908). IEEE, Los Alamitos, CA, 1--4."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744900"},{"volume-title":"Proceedings of the Asia and South Pacific and Design Automation Conference (ASP-DAC\u201911)","author":"Lu W.","key":"e_1_2_1_23_1","unstructured":"W. Lu , K.-H. Kim , T. Chang , and S. Gaba . 2011. Two-terminal resistive switches (memristors) for memory and logic applications . In Proceedings of the Asia and South Pacific and Design Automation Conference (ASP-DAC\u201911) . W. Lu, K.-H. Kim, T. Chang, and S. Gaba. 2011. Two-terminal resistive switches (memristors) for memory and logic applications. In Proceedings of the Asia and South Pacific and Design Automation Conference (ASP-DAC\u201911)."},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874728"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jneumeth.2007.09.022"},{"key":"e_1_2_1_26_1","volume-title":"Proceedings of the Asia and South Pacific and Design Automation Conference (ASP-DAC\u201916)","author":"Ni Leibin","year":"2016","unstructured":"Leibin Ni , Yuhao Wang , Hao Yu , Wei Yang , Chuliang Weng , and Junfeng Zhao . 2016 . An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar . In Proceedings of the Asia and South Pacific and Design Automation Conference (ASP-DAC\u201916) . Leibin Ni, Yuhao Wang, Hao Yu, Wei Yang, Chuliang Weng, and Junfeng Zhao. 2016. An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. In Proceedings of the Asia and South Pacific and Design Automation Conference (ASP-DAC\u201916)."},{"volume-title":"Proceedings of the Conference on Design, Automation, and Test in Europe. 1637--1642","author":"Park Sunghyun","key":"e_1_2_1_27_1","unstructured":"Sunghyun Park , Masood Qazi , Li-Shiuan Peh , and Anantha P. Chandrakasan . 2013. 40.4 fJ\/bit\/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS . In Proceedings of the Conference on Design, Automation, and Test in Europe. 1637--1642 . Sunghyun Park, Masood Qazi, Li-Shiuan Peh, and Anantha P. Chandrakasan. 2013. 40.4 fJ\/bit\/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS. In Proceedings of the Conference on Design, Automation, and Test in Europe. 1637--1642."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2180441"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405710"},{"key":"e_1_2_1_30_1","volume-title":"Kaushik Roy, and Mrigank Sharad.","author":"Srimani Tathagata","year":"2015","unstructured":"Tathagata Srimani , Bibhas Manna , Anand Kumar Mukhopadhyay , Kaushik Roy, and Mrigank Sharad. 2015 . Energy efficient and high performance current-mode neural network circuit using memristors and digitally assisted analog CMOS neurons. arXiv:1511.09085. Tathagata Srimani, Bibhas Manna, Anand Kumar Mukhopadhyay, Kaushik Roy, and Mrigank Sharad. 2015. Energy efficient and high performance current-mode neural network circuit using memristors and digitally assisted analog CMOS neurons. arXiv:1511.09085."},{"key":"e_1_2_1_31_1","doi-asserted-by":"crossref","unstructured":"Dmitri B. Strukov Gregory S. Snider Duncan R. Stewart and R. Stanley Williams. 2008. The missing memristor found. Nature 453 7191 80--83.  Dmitri B. Strukov Gregory S. Snider Duncan R. Stewart and R. Stanley Williams. 2008. The missing memristor found. Nature 453 7191 80--83.","DOI":"10.1038\/nature06932"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1018628609742"},{"key":"e_1_2_1_33_1","unstructured":"T. Tan and Z. Sun. 2010. CASIA-FingerprintV5. Available at http:\/\/biometrics.idealtest.org\/.  T. Tan and Z. Sun. 2010. CASIA-FingerprintV5. Available at http:\/\/biometrics.idealtest.org\/."},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2447531"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265754"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.58337"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2008.4687366"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1016\/0169-7439(87)80084-9"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1996.8.7.1341"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2008.79"},{"volume-title":"Design Exploration of Emerging Nano-scale Non-volatile Memory","author":"Yu Hao","key":"e_1_2_1_42_1","unstructured":"Hao Yu and Yuhao Wang . 2014. Design Exploration of Emerging Nano-scale Non-volatile Memory . Springer . Hao Yu and Yuhao Wang. 2014. Design Exploration of Emerging Nano-scale Non-volatile Memory. Springer."}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2996192","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2996192","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:10Z","timestamp":1750220590000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2996192"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3,17]]},"references-count":41,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,7,31]]}},"alternative-id":["10.1145\/2996192"],"URL":"https:\/\/doi.org\/10.1145\/2996192","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2017,3,17]]},"assertion":[{"value":"2016-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-03-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}