{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:10:30Z","timestamp":1750306230186,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2016,12,9]],"date-time":"2016-12-09T00:00:00Z","timestamp":1481241600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2017,3,31]]},"abstract":"<jats:p>Commercial off-the-shelf (COTS) Field-Programmable Gate Arrays (FPGAs) are becoming increasingly powerful. In addition to their huge hardware resources, they are also integrated into complete systems on chips (SOCs), e.g., in the latest Xilinx Zynq or Altera Stratix platforms. However, cooperation between FPGAs and their surroundings, and the flexibility of hardware task management could still be improved. For instance, mechanisms have yet to be automated to allow multi-user approaches. A reconfigurable resource can be shared between applications or users only if it has a context-switch ability allowing applications to be paused and resumed in response to system demands. Here, we present a high-level synthesis (HLS) design flow producing a context-switch-capable circuit. The design flow manipulates the intermediate representation of an HLS tool to build the context extraction mechanism and to optimize performance for the circuit produced. The method is based on efficient checkpoint selection and insertion of a powerful scan-chain into the initial circuit. This scan-chain can extract flip-flops or memory content. Experiments with the system produced show that it has a low hardware overhead for many benchmark applications, and that the hardware added has a negligible impact on application performance. Comparisons with current standard methods highlight the efficiency of our contributions.<\/jats:p>","DOI":"10.1145\/2996199","type":"journal-article","created":{"date-parts":[[2016,12,9]],"date-time":"2016-12-09T17:26:14Z","timestamp":1481304374000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow"],"prefix":"10.1145","volume":"10","author":[{"given":"Alban","family":"Bourge","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, TIMA F-38000, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Olivier","family":"Muller","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, TIMA F-38000, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fr\u00e9d\u00e9ric","family":"Rousseau","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, TIMA F-38000, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,12,9]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046212"},{"key":"e_1_2_1_2_1","doi-asserted-by":"crossref","unstructured":"Brandon Blodget Philip James-Roxby Eric Keller Scott McMillan and Prasanna Sundararajan. 2003. A Self-reconfiguring Platform. Springer Berlin 565--574.  Brandon Blodget Philip James-Roxby Eric Keller Scott McMillan and Prasanna Sundararajan. 2003. A Self-reconfiguring Platform. Springer Berlin 565--574.","DOI":"10.1007\/978-3-540-45234-8_55"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.8"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.25"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2012.2188805"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1287\/moor.4.3.233"},{"volume-title":"Introduction to Algorithms","author":"Cormen Thomas H.","key":"e_1_2_1_7_1","unstructured":"Thomas H. Cormen , Charles E. Leiserson , Ronald L. Rivest , Clifford Stein , and others. 2001. Introduction to Algorithms . Vol. 2 . MIT Press and McGraw-Hill . Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest, Clifford Stein, and others. 2001. Introduction to Algorithms. Vol. 2. MIT Press and McGraw-Hill."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-013-0884-0"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/568522.568525"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2209285.2209287"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759297"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02577777"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391962.1391964"},{"volume-title":"Proceedings of the 29th Annual International Symposium on Fault-Tolerant Computing. Digest of Papers. IEEE, 260--267","author":"Hamzaoglu Ilker","key":"e_1_2_1_14_1","unstructured":"Ilker Hamzaoglu and Janak H. Patel . 1999. Reducing test application time for full scan embedded cores . In Proceedings of the 29th Annual International Symposium on Fault-Tolerant Computing. Digest of Papers. IEEE, 260--267 . Ilker Hamzaoglu and Janak H. Patel. 1999. Reducing test application time for full scan embedded cores. In Proceedings of the 29th Annual International Symposium on Fault-Tolerant Computing. Digest of Papers. IEEE, 260--267."},{"key":"e_1_2_1_15_1","first-page":"740","article-title":"Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis","volume":"4","author":"Hara Yuko","year":"2009","unstructured":"Yuko Hara , Hiroyuki Tomiyama , Shinya Honda , and Hiroaki Takada . 2009 . Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis . Information and Media Technologies 4 , 4 (2009), 740 -- 752 . Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada. 2009. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. Information and Media Technologies 4, 4 (2009), 740--752.","journal-title":"Information and Media Technologies"},{"key":"e_1_2_1_16_1","volume-title":"Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann","author":"Hauck Scott","year":"2010","unstructured":"Scott Hauck and Andre DeHon . 2010 . Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann , San Francisco, CA . Scott Hauck and Andre DeHon. 2010. Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann, San Francisco, CA."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645516"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2012.2193660"},{"key":"e_1_2_1_19_1","volume-title":"FPL","author":"Kalte Heiko","year":"2005","unstructured":"Heiko Kalte and Mario Porrmann . 2005. Context saving and restoring for multitasking in reconfigurable systems . In FPL , 2005 . IEEE. Heiko Kalte and Mario Porrmann. 2005. Context saving and restoring for multitasking in reconfigurable systems. In FPL, 2005. IEEE."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216950"},{"key":"e_1_2_1_21_1","volume-title":"Hutchings","author":"Landaker Wesley J.","year":"2002","unstructured":"Wesley J. Landaker , Michael J. Wirthlin , and Brad L . Hutchings . 2002 . Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. Springer , Berlin, 806--815. Wesley J. Landaker, Michael J. Wirthlin, and Brad L. Hutchings. 2002. Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. Springer, Berlin, 806--815."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/795659.795885"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1281700.1281702"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/649057"},{"key":"e_1_2_1_25_1","volume-title":"Proceedings of the 1995 IEEE\/ACM International Conference on Computer-aided Design. IEEE Computer Society, 528--533","author":"Lin Chih-Chang","year":"1995","unstructured":"Chih-Chang Lin , Mike Tien-Chien Lee , Malgorzata Marek-Sadowska , and Kuang-Chien Chen . 1995 . Cost-free scan: A low-overhead scan path design methodology . In Proceedings of the 1995 IEEE\/ACM International Conference on Computer-aided Design. IEEE Computer Society, 528--533 . Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, and Kuang-Chien Chen. 1995. Cost-free scan: A low-overhead scan path design methodology. In Proceedings of the 1995 IEEE\/ACM International Conference on Computer-aided Design. IEEE Computer Society, 528--533."},{"key":"e_1_2_1_26_1","volume-title":"DATE","author":"Mignolet J.-Y.","year":"2003","unstructured":"J.-Y. Mignolet , Vincent Nollet , Paul Coene , Diederik Verkest , Serge Vernalde , and Rudy Lauwereins . 2003. Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip . In DATE 2003 . IEEE , 986--991. J.-Y. Mignolet, Vincent Nollet, Paul Coene, Diederik Verkest, Serge Vernalde, and Rudy Lauwereins. 2003. Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip. In DATE 2003. IEEE, 986--991."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068722"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.10.002"},{"key":"e_1_2_1_29_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 352--357","author":"Reorda M. Sonza","year":"2009","unstructured":"M. Sonza Reorda , Massimo Violante , Cristina Meinhardt , and Ricardo Reis . 2009 . A low-cost SEE mitigation solution for soft-processors embedded in systems on programmable chips . In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 352--357 . M. Sonza Reorda, Massimo Violante, Cristina Meinhardt, and Ricardo Reis. 2009. A low-cost SEE mitigation solution for soft-processors embedded in systems on programmable chips. In Proceedings of the Conference on Design, Automation and Test in Europe. European Design and Automation Association, 352--357."},{"key":"e_1_2_1_30_1","volume-title":"FCCM","author":"Stephen","year":"1998","unstructured":"Stephen M. Scalera and J\u00f3se R. Vazquez. 1998. The design and implementation of a context switching FPGA . In FCCM 1998 . IEEE, 78--85. Stephen M. Scalera and J\u00f3se R. Vazquez. 1998. The design and implementation of a context switching FPGA. In FCCM 1998. IEEE, 78--85."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.22"},{"key":"e_1_2_1_32_1","volume-title":"IEE Proceedings. IET.","author":"Sedcole Pete","year":"2006","unstructured":"Pete Sedcole , Brandon Blodget , Tobias Becker , James Anderson , and Patrick Lysaght . 2006 . Modular dynamic reconfiguration in Virtex FPGAs. In Computers and Digital Techniques , IEE Proceedings. IET. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, and Patrick Lysaght. 2006. Modular dynamic reconfiguration in Virtex FPGAs. In Computers and Digital Techniques, IEE Proceedings. IET."},{"key":"e_1_2_1_33_1","doi-asserted-by":"crossref","unstructured":"H. Simmler L. Levinson and R. M\u00e4nner. 2000. Multitasking on FPGA Coprocessors. Springer Berlin 121--130.   H. Simmler L. Levinson and R. M\u00e4nner. 2000. Multitasking on FPGA Coprocessors. Springer Berlin 121--130.","DOI":"10.1007\/3-540-44614-1_13"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.105"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.5555\/549928.795737"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303106"},{"key":"e_1_2_1_37_1","volume-title":"FPL","author":"Wheeler Timothy","year":"2001","unstructured":"Timothy Wheeler , Paul Graham , Brent Nelson , and Brad Hutchings . 2001. Using design-level scan to improve FPGA design observability and controllability for functional verification . In FPL , 2001 . Springer , 483--492. Timothy Wheeler, Paul Graham, Brent Nelson, and Brad Hutchings. 2001. Using design-level scan to improve FPGA design observability and controllability for functional verification. In FPL, 2001. Springer, 483--492."},{"key":"e_1_2_1_38_1","unstructured":"Xilinx. 2010. Partial Reconfiguration User Guide. UG702. http:\/\/www.xilinx.com.  Xilinx. 2010. Partial Reconfiguration User Guide. UG702. http:\/\/www.xilinx.com."},{"key":"e_1_2_1_39_1","unstructured":"Xilinx. 2014. 7 Series FPGAs Configurable Logic Block. UG474.  Xilinx. 2014. 7 Series FPGAs Configurable Logic Block. UG474."},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/312808"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2996199","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2996199","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:10Z","timestamp":1750220590000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2996199"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12,9]]},"references-count":40,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2017,3,31]]}},"alternative-id":["10.1145\/2996199"],"URL":"https:\/\/doi.org\/10.1145\/2996199","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"type":"print","value":"1936-7406"},{"type":"electronic","value":"1936-7414"}],"subject":[],"published":{"date-parts":[[2016,12,9]]},"assertion":[{"value":"2015-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-12-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}