{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,27]],"date-time":"2025-09-27T13:43:38Z","timestamp":1758980618402,"version":"3.41.0"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,7,7]],"date-time":"2017-07-07T00:00:00Z","timestamp":1499385600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1149285"],"award-info":[{"award-number":["CNS-1149285"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2017,8,31]]},"abstract":"<jats:p>Serial arithmetic has been shown to offer attractive advantages in area for field-programmable gate array (FPGA) datapaths but suffers from a significant reduction in throughput compared to traditional bit-parallel designs. In this work, we perform a performance and trade-off analysis that counterintuitively shows that, despite the decreased throughput of individual serial operators, replication of serial arithmetic can provide a 2.1 \u00d7 average increase in throughput compared to bit-parallel pipelines for common FPGA applications. We complement this analysis with a novel SerDes architecture that enables existing FPGA pipelines to be replaced with serial logic with potentially higher throughput. We also present a serialized sliding-window architecture that improves average throughput 2.4 \u00d7 compared to existing bit-parallel work.<\/jats:p>","DOI":"10.1145\/2996459","type":"journal-article","created":{"date-parts":[[2017,7,7]],"date-time":"2017-07-07T12:17:18Z","timestamp":1499429838000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Serial Arithmetic Strategies for Improving FPGA Throughput"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5727-1758","authenticated-orcid":false,"given":"Aaron","family":"Landy","sequence":"first","affiliation":[{"name":"University of Florida, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Greg","family":"Stitt","sequence":"additional","affiliation":[{"name":"University of Florida, Gainesville, FL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,7,7]]},"reference":[{"volume-title":"CA 95134. Retrieved","year":"2017","key":"e_1_2_1_1_1"},{"volume-title":"Proceedings of the PLD Conference.","year":"1993","author":"Andraka R. J.","key":"e_1_2_1_2_1"},{"volume-title":"Technique for converting either way between a plurality of N synchronized serial bit streams and a parallel TDM format. Retrieved","year":"2017","author":"Baylock G. A.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","unstructured":"H. Charych and S. Chattopadhya. 1992. Serial-to-parallel and parallel-to-serial converter. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US5134702. US Patent 5 134 702.  H. Charych and S. Chattopadhya. 1992. Serial-to-parallel and parallel-to-serial converter. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US5134702. US Patent 5 134 702."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675239"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380445.2380491"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/82.204111"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1989.72812"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1990.145489"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.44"},{"volume-title":"Proceedings of the 8th European Solid-State Circuits Conference (ESSCIRC\u201982)","author":"Denyer P. B.","key":"e_1_2_1_11_1"},{"key":"e_1_2_1_12_1","unstructured":"J. E. Elliott and J. R. Elliott. 1983. Parallel to serial converter. (March 22 1983). Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US4377806. US Patent 4 377 806.  J. E. Elliott and J. R. Elliott. 1983. Parallel to serial converter. (March 22 1983). Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US4377806. US Patent 4 377 806."},{"key":"e_1_2_1_13_1","unstructured":"M. Flavio and P. Giovanni. 1975. Multiplexing\/demultiplexing network with series\/parallel conversion for TDM system. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US3914553. US Patent 3 914 553.  M. Flavio and P. Giovanni. 1975. Multiplexing\/demultiplexing network with series\/parallel conversion for TDM system. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US3914553. US Patent 3 914 553."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145704"},{"volume":"1","volume-title":"Proceedings of the IEEE International Symposium on Circuits and Systems.","author":"Hartley R.","key":"e_1_2_1_15_1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/31.55029"},{"key":"e_1_2_1_17_1","unstructured":"R. I. Hartley P. F. Corbett F. F. Yassa and S. E. Noujaim. 1990. To-digit-serial converters for systems processing data in digit-serial format. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US4942396. US Patent 4 942 396.  R. I. Hartley P. F. Corbett F. F. Yassa and S. E. Noujaim. 1990. To-digit-serial converters for systems processing data in digit-serial format. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US4942396. US Patent 4 942 396."},{"key":"e_1_2_1_18_1","unstructured":"E. Herrera and F. Merrell. 1966. Serial-parallel mode digital converter. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US3267460. US Patent 3 267 460.  E. Herrera and F. Merrell. 1966. Serial-parallel mode digital converter. Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US3267460. US Patent 3 267 460."},{"key":"e_1_2_1_19_1","unstructured":"G. Hush J. Baker and T. Voshell. 1997. Serial to parallel conversion with phase locked loop. (Jan. 28 1997). Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US5598156. US Patent 5 598 156.  G. Hush J. Baker and T. Voshell. 1997. Serial to parallel conversion with phase locked loop. (Jan. 28 1997). Retrieved March 3 2017 from http:\/\/www.google.com\/patents\/US5598156. US Patent 5 598 156."},{"volume-title":"Proceedings of the 10th International Conference on Microelectronics (ICM\u201998)","author":"Khalil A. H.","key":"e_1_2_1_20_1"},{"volume-title":"Parallel to serial digital converter. Retrieved","year":"2017","author":"Koenig H. J.","key":"e_1_2_1_21_1"},{"volume-title":"Proceedings of the Midwest Symposium on Circuits and Systems. 46--49","author":"Landry R.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.53"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.17"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1976.1093315"},{"volume-title":"FPGA implemented bit-serial multiplier and infinite impulse response filter. (June 24","year":"2003","author":"Miller A. J.","key":"e_1_2_1_26_1"},{"volume-title":"Proceedings of the 41st Annual International Symposium on Computer Architecture (ISCA\u201914)","author":"Putnam A.","key":"e_1_2_1_27_1"},{"volume":"1","volume-title":"Proceedings of the IEEE 39th Midwest Symposium on Circuits and Systems","author":"Rao V. M.","key":"e_1_2_1_28_1"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/SSST.1994.287878"},{"volume-title":"The Scientist and Engineer\u2019s Guide to Digital Signal Processing","author":"Smith S. W.","key":"e_1_2_1_30_1"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-e.1987.0046"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676865"},{"volume-title":"7 Series FPGAs Configurable Logic Block (1.5 ed.). Xilinx. Retrieved","year":"2017","key":"e_1_2_1_33_1"},{"volume-title":"Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs (UG768) (14.7 ed.). Xilinx. Retrieved","year":"2017","key":"e_1_2_1_34_1"},{"volume-title":"Xilinx Constraints Guide (UG625) (14.5 ed.). Xilinx. Retrieved","year":"2017","key":"e_1_2_1_35_1"},{"volume-title":"7 Series FPGAs SelectIO Resources (1.6 ed.). Xilinx. Retrieved","year":"2017","key":"e_1_2_1_36_1"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/26.8928"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2996459","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2996459","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2996459","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:23:11Z","timestamp":1750220591000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2996459"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7,7]]},"references-count":37,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,8,31]]}},"alternative-id":["10.1145\/2996459"],"URL":"https:\/\/doi.org\/10.1145\/2996459","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2017,7,7]]},"assertion":[{"value":"2016-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-07-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}