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As computer architectures evolve toward heterogeneous multi-cores composed of a mix of cores and hardware accelerators, designing hardware accelerators for ML techniques can simultaneously achieve high efficiency and broad application scope.<\/jats:p><jats:p>While efficient computational primitives are important for a hardware accelerator, inefficient memory transfers can potentially void the throughput, energy, or cost advantages of accelerators, that is, an Amdahl's law effect, and thus, they should become a first-order concern, just like in processors, rather than an element factored in accelerator design on a second step. In this article, we introduce a series of hardware accelerators (i.e., the DianNao family) designed for ML (especially neural networks), with a special emphasis on the impact of memory on accelerator design, performance, and energy. We show that, on a number of representative neural network layers, it is possible to achieve a speedup of 450.65x over a GPU, and reduce the energy by 150.31x on average for a 64-chip DaDianNao system (a member of the DianNao family).&lt;!-- END_PAGE_1 --&gt;<\/jats:p>","DOI":"10.1145\/2996864","type":"journal-article","created":{"date-parts":[[2016,10,31]],"date-time":"2016-10-31T12:29:14Z","timestamp":1477916954000},"page":"105-112","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":189,"title":["DianNao family"],"prefix":"10.1145","volume":"59","author":[{"given":"Yunji","family":"Chen","sequence":"first","affiliation":[{"name":"ICT, CAS, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tianshi","family":"Chen","sequence":"additional","affiliation":[{"name":"ICT, CAS, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhiwei","family":"Xu","sequence":"additional","affiliation":[{"name":"ICT, CAS, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ninghui","family":"Sun","sequence":"additional","affiliation":[{"name":"ICT, CAS, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Olivier","family":"Temam","sequence":"additional","affiliation":[{"name":"Inria Saclay, France"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2016,10,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2009.34"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815993"},{"key":"e_1_2_1_3_1","doi-asserted-by":"crossref","DOI":"10.1002\/9781118676998","volume-title":"Algorithmic Trading: Winning Strategies and Their Rationale","author":"Chan E.","year":"2013","unstructured":"Chan , E. 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Maeda, N., Komatsu, S., Morimoto, M., Shimazaki, Y. A 0.41 \u00b5a standby leakage 32 kb embedded SRAM with low-voltage resume-standby utilizing all digital current comparator in 28 nm hkmg CMOS. In International Symposium on VLSI Circuits (VLSIC), 2012."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2133382.2133388"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2010.2100802"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537602"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR.2006.961"},{"key":"e_1_2_1_35_1","first-page":"285","article-title":"Dark silicon and the internet. In EE Times \"Designing with ARM","volume":"26","author":"Muller M","unstructured":"Muller , M . Dark silicon and the internet. In EE Times \"Designing with ARM \" Virtual Conference , 26 , 70(2010), 285 -- 288 . Muller, M. Dark silicon and the internet. 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