{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:10:49Z","timestamp":1767262249193,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2016,10,19]],"date-time":"2016-10-19T00:00:00Z","timestamp":1476835200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Minist\u00e8re de l'\u00c9conomie, des Finances et de l'Industrie","award":["PIA-FSN2 n P3425-146798"],"award-info":[{"award-number":["PIA-FSN2 n P3425-146798"]}]},{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/K011626\/1"],"award-info":[{"award-number":["EP\/K011626\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,10,19]]},"DOI":"10.1145\/2997465.2997472","type":"proceedings-article","created":{"date-parts":[[2016,10,20]],"date-time":"2016-10-20T15:58:54Z","timestamp":1476979134000},"page":"67-76","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor"],"prefix":"10.1145","author":[{"given":"Hamza","family":"Rihani","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, VERIMAG, Grenoble, France"}]},{"given":"Matthieu","family":"Moy","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, VERIMAG, Grenoble, France"}]},{"given":"Claire","family":"Maiza","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes, CNRS, VERIMAG, Grenoble, France"}]},{"given":"Robert I.","family":"Davis","sequence":"additional","affiliation":[{"name":"University of York, UK, INRIA, France"}]},{"given":"Sebastian","family":"Altmeyer","sequence":"additional","affiliation":[{"name":"University of Luxembourg, Luxembourg"}]}],"member":"320","published-online":{"date-parts":[[2016,10,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2834848.2834862"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-012-9152-2"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/1927882.1927891"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1007\/978-1-4020-6254-4_2","volume-title":"Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems: Proceedings of the GM R&D Workshop","author":"Berry G.","year":"2007","unstructured":"G. Berry . Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems: Proceedings of the GM R&D Workshop , chapter SCADE: Synchronous Design and Validation of Embedded Control Software, pages 19 -- 33 . 2007 . G. Berry. Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems: Proceedings of the GM R&D Workshop, chapter SCADE: Synchronous Design and Validation of Embedded Control Software, pages 19--33. 2007."},{"issue":"2","key":"e_1_3_2_1_5_1","first-page":"1","article-title":"From dataflow specification to multiprocessor partitioned time-triggered real-time implementation","volume":"2","author":"Carle T.","year":"2015","unstructured":"T. Carle , D. Potop-Butucaru , Y. Sorel , and D. Lesens . From dataflow specification to multiprocessor partitioned time-triggered real-time implementation . LITES , 2 ( 2 ):01: 1 -- 01 :30, 2015 . T. Carle, D. Potop-Butucaru, Y. Sorel, and D. Lesens. From dataflow specification to multiprocessor partitioned time-triggered real-time implementation. LITES, 2(2):01:1--01:30, 2015.","journal-title":"LITES"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/2971808.2971849"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-015-9229-9"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2685342.2685344"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/2616606.2616725"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-015-9227-y"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.97300"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-014-9211-y"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2834848.2834854"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2014.20"},{"key":"e_1_3_2_1_15_1","volume-title":"WCET","author":"N\u00e9lis V.","year":"2016","unstructured":"V. N\u00e9lis , P. M. Yomsi , and L. M. Pinho . The variability of application execution times on a multi-core platform \". In WCET 2016 . V. N\u00e9lis, P. M. Yomsi, and L. M. Pinho. The variability of application execution times on a multi-core platform\". In WCET 2016."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6926012"},{"key":"e_1_3_2_1_17_1","first-page":"741","volume-title":"DATE","author":"Pellizzoni R.","year":"2010","unstructured":"R. Pellizzoni , A. Schranzhofer , J.-J. Chen , M. Caccamo , and L. Thiele . Worst case delay analysis for memory interference in multicore systems . In DATE 2010 , pages 741 -- 746 . R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele. Worst case delay analysis for memory interference in multicore systems. In DATE 2010, pages 741--746."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2013.6531101"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086713"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2010.24"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"e_1_3_2_1_23_1","volume-title":"IDEA","author":"Walter J.","year":"2015","unstructured":"J. Walter and W. Nebel . Energy--aware mapping and scheduling of large--scale macro data--flow applications . In IDEA 2015 . J. Walter and W. Nebel. Energy--aware mapping and scheduling of large--scale macro data--flow applications. In IDEA 2015."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347389"}],"event":{"name":"RTNS '16: 24th International Conference on Real-Time Networks and Systems","sponsor":["REGIONB Region Bretagne"],"location":"Brest France","acronym":"RTNS '16"},"container-title":["Proceedings of the 24th International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2997465.2997472","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2997465.2997472","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:50:31Z","timestamp":1750218631000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2997465.2997472"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10,19]]},"references-count":23,"alternative-id":["10.1145\/2997465.2997472","10.1145\/2997465"],"URL":"https:\/\/doi.org\/10.1145\/2997465.2997472","relation":{},"subject":[],"published":{"date-parts":[[2016,10,19]]},"assertion":[{"value":"2016-10-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}