{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:10:04Z","timestamp":1750306204224,"version":"3.41.0"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,4,20]],"date-time":"2017-04-20T00:00:00Z","timestamp":1492646400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Basic Research Program of China","doi-asserted-by":"crossref","award":["2011CB302503"],"award-info":[{"award-number":["2011CB302503"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["61274030, 61432017, 61504153 and 61532017"],"award-info":[{"award-number":["61274030, 61432017, 61504153 and 61532017"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"<jats:p>Phase change memory (PCM) is a promising alternative to Dynamic Random Access Memory (DRAM) as main memory due to its merits of high density and low leakage power. Multi-level Cell (MLC) PCM is more attractive than Single-level Cell (SLC) PCM, because it can store multiple bits per cell to achieve higher density and lower per-bit cost. With the iterative program-verify write technique, MLC PCM writes demand at much higher power than DRAM writes, while the power supply system of MLC memory system is similar to that of DRAM, and the power capability is limited. The incompatibility of high write power and limited power budget results in the degradation of the write throughput and performance in MLC PCM. In this work, we investigate both write scheduling policy and power management to improve the MLC power utility and alleviate the negative impacts induced by high write power. We identify the power-utility-driven write scheduling as an online bin-packing problem and then derive a power-utility-driven scheduling (PUDS) policy from the First Fit algorithm to improve the write power usage. Based on the ramp-down characteristic of the SET pulse (the pulse changes the PCM to high resistance), we propose the SET Power Amortization (SPA) policy, which proactively reclaims the power tokens at the intra-SET level to promote the power utilization. Our experimental results demonstrate that the PUDS and SPA respectively achieve 24% and 27% performance improvement over the state-of-the-art power management technique, and the PUDS8SPA has an overall 31% improvement of the power utility and 50% increase of performance compared to the baseline system.<\/jats:p>","DOI":"10.1145\/2997648","type":"journal-article","created":{"date-parts":[[2017,4,20]],"date-time":"2017-04-20T12:05:21Z","timestamp":1492689921000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Power-Utility-Driven Write Management for MLC PCM"],"prefix":"10.1145","volume":"13","author":[{"given":"Bing","family":"Li","sequence":"first","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences; University of Chinese Academy of Sciences"}]},{"given":"YU","family":"HU","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences"}]},{"given":"Ying","family":"Wang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences"}]},{"given":"Jing","family":"Ye","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences"}]},{"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences"}]}],"member":"320","published-online":{"date-parts":[[2017,4,20]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOMW.2010.5700271"},{"volume-title":"Proceedings of the 2015 Symposium on VLSI Technology (VLSI Technology). T100--T101","author":"Chien W. C.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"e_1_2_1_5_1","first-page":"7","article-title":"NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory","volume":"31","author":"Dong Xiangyu","year":"2012","journal-title":"IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155642"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"volume-title":"Semiconductor Industry Association","year":"2015","author":"International Technology","key":"e_1_2_1_8_1"},{"volume-title":"Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann","year":"2010","author":"Jacob Bruce","key":"e_1_2_1_9_1"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.10"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749742"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2310497"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/777092.777205"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"volume-title":"Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA). IEEE, 25--34","year":"2013","author":"Lee Yebin","key":"e_1_2_1_16_1"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2012.05.002"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541957"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.45"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"e_1_2_1_21_1","unstructured":"Technology Inc. Micron. 2016. DDR4: Advantages of migrating from DDR3. Retrieved from https:\/\/www.micron.com\/products\/dram\/ddr3-to-ddr4.  Technology Inc. Micron. 2016. DDR4: Advantages of migrating from DDR3. Retrieved from https:\/\/www.micron.com\/products\/dram\/ddr3-to-ddr4."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382128"},{"key":"e_1_2_1_24_1","unstructured":"Ron Neale. 2015. IBM solves PCM problems with projections. Retrieved from http:\/\/www.eetimes.com\/author.asp?doc_id&equals;1327596.  Ron Neale. 2015. IBM solves PCM problems with projections. Retrieved from http:\/\/www.eetimes.com\/author.asp?doc_id&equals;1327596."},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418973"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.3626047"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703444"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724687"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937569"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582108"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337203"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416645"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815981"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.524.0465"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.4"},{"key":"e_1_2_1_38_1","unstructured":"Electronics Co. Ltd. Samsung. 2013. Samsung DDR4 SDRAM. Retrieved from http:\/\/159.226.251.229\/videoplayer\/DDR4_Brochure-0.pdf.  Electronics Co. Ltd. Samsung. 2013. Samsung DDR4 SDRAM. Retrieved from http:\/\/159.226.251.229\/videoplayer\/DDR4_Brochure-0.pdf."},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1038\/ncomms5314"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540726"},{"key":"e_1_2_1_41_1","first-page":"12","article-title":"Phase change memory","volume":"98","author":"Philip Wong H. S.","year":"2010","journal-title":"Proc. IEEE"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2053565"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337163"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2010.5470451"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2997648","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2997648","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:50:32Z","timestamp":1750218632000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2997648"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4,20]]},"references-count":45,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,7,31]]}},"alternative-id":["10.1145\/2997648"],"URL":"https:\/\/doi.org\/10.1145\/2997648","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2017,4,20]]},"assertion":[{"value":"2015-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-04-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}