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Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"<jats:p>The non-volatile memory (NVM) has the merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory allocators. However, traditional memory allocators designed with in-place data writes are not appropriate for the non-volatile main memory (NVRAM) due to the limited endurance. In this article, first, we quantitatively analyze the wear-oblivious of DRAM-oriented designed allocator\u2014glibc malloc and the inefficiency of wear-conscious allocator NVMalloc. Then, we propose WAlloc, an efficient wear-aware manual memory allocator designed for NVRAM: (1) decouples metadata and data management; (2) distinguishes metadata with volatility; (3) redirects the data writes around to achieve wear-leveling; (4) redesigns an efficient and effective NVM copy mechanism, bypassing the CPU cache partially and prefetching data explicitly. Finally, experimental results show that the wear-leveling of WAlloc outperforms that of NVMalloc about 30% and 60% under random workloads and well-distributed workloads, respectively. Besides, WAlloc reduces the average data memory writes in 64 bytes block by 1.5 times comparing with glibc malloc. With the fulfillment of data persistency, cache bypassing NVM copy is better than cache line flushing NVM copy with performance improvement circa 14%.<\/jats:p>","DOI":"10.1145\/2997651","type":"journal-article","created":{"date-parts":[[2017,4,14]],"date-time":"2017-04-14T12:18:48Z","timestamp":1492172328000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Redesign the Memory Allocator for Non-Volatile Main Memory"],"prefix":"10.1145","volume":"13","author":[{"given":"Songping","family":"Yu","sequence":"first","affiliation":[{"name":"National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nong","family":"Xiao","sequence":"additional","affiliation":[{"name":"National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mingzhu","family":"Deng","sequence":"additional","affiliation":[{"name":"National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fang","family":"Liu","sequence":"additional","affiliation":[{"name":"National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Chen","sequence":"additional","affiliation":[{"name":"National University of Defense Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2017,4,14]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2318857.2254766"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.2200\/S00516ED2V01Y201306CAC024"},{"key":"e_1_2_1_3_1","volume-title":"Memory Management: Algorithms and Implementation in C\/C++","author":"Blunden Bill","year":"2003","unstructured":"Bill Blunden . 2003 . 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Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling . In Proceedings of FAST 2014. 61--74. Jaeyong Jeong, Sangwook Shane Hahn, Sungjin Lee, and Jihong Kim. 2014. Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling. In Proceedings of FAST 2014. 61--74."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169027"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250880"},{"key":"e_1_2_1_24_1","volume-title":"Proceedings of the Conference on Design, Automation 8 Test in Europe, 89","author":"Li Qingan","year":"2014","unstructured":"Qingan Li , Yanxiang He , Yong Chen , Chun Jason Xue , Nan Jiang , and Chao Xu . 2014 . A wear-leveling-aware dynamic stack for PCM memory in embedded systems . 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