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In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in the pipelanes of a configurable VLIW processor. The first uses idle issue slots within a period of time to execute extra instructions considering distinct application phases. The second works at a finer grain, adaptively exploiting idle functional units at run-time. However, some applications present high instruction-level parallelism (ILP), so the ability to provide fault tolerance is reduced: less functional units will be idle, decreasing the number of potential duplicated instructions. The third approach attacks this issue by dynamically reducing ILP according to a configurable threshold, increasing fault tolerance at the cost of performance. While the first two approaches achieve significant fault coverage with minimal area and power overhead for applications with low ILP, the latter improves fault tolerance with low performance degradation. All approaches are evaluated considering area, performance, power dissipation, and error coverage.<\/jats:p>","DOI":"10.1145\/3001935","type":"journal-article","created":{"date-parts":[[2017,1,9]],"date-time":"2017-01-09T13:19:08Z","timestamp":1483967948000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors"],"prefix":"10.1145","volume":"13","author":[{"given":"Anderson L.","family":"Sartor","sequence":"first","affiliation":[{"name":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil"}]},{"given":"Arthur F.","family":"Lorenzon","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil"}]},{"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil"}]},{"given":"Fernanda","family":"Kastensmidt","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul, Porto Alegre, Brazil"}]},{"given":"Stephan","family":"Wong","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Delft, The Netherlands"}]},{"given":"Antonio C. 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